llvm-6502/test/CodeGen/Mips/inlineasm-operand-code.ll
Eric Christopher 6ab75b4dcb Add support for the mips inline asm 'm' output modifier.
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30 19:05:19 +00:00

34 lines
837 B
LLVM

; Positive test for inline register constraints
;
; RUN: llc -march=mipsel < %s | FileCheck %s
define i32 @main() nounwind {
entry:
; X with -3
;CHECK: #APP
;CHECK: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
;CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) nounwind
; x with -3
;CHECK: #APP
;CHECK: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
;CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) nounwind
; d with -3
;CHECK: #APP
;CHECK: addi ${{[0-9]+}},${{[0-9]+}},-3
;CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) nounwind
; m with -3
;CHECK: #APP
;CHECK: addi ${{[0-9]+}},${{[0-9]+}},-4
;CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) nounwind
ret i32 0
}