Craig Topper 01c99892ca [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225099 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-03 00:00:20 +00:00
..
avx-512.txt	AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction	2014-10-26 09:52:24 +00:00
fp-stack.txt	Add two fp test cases I missed in my previous commit.	2013-12-31 23:15:19 +00:00
hex-immediates.txt	llvm-mc: Add option for prefering hex format disassembly.	2014-06-11 20:26:40 +00:00
intel-syntax-32.txt
intel-syntax.txt	Fixing Intel format of the vshufpd instruction.	2013-09-27 01:44:23 +00:00
invalid-VEX-vvvv.txt
lit.local.cfg	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
marked-up.txt
missing-sib.txt	Test case for r204305.	2014-03-20 06:45:10 +00:00
moffs.txt	[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.	2015-01-02 07:02:25 +00:00
padlock.txt	Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.	2014-02-19 05:34:21 +00:00
prefixes.txt	[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.	2015-01-03 00:00:20 +00:00
simple-tests.txt	Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.	2014-01-01 15:29:32 +00:00
truncated-input.txt
x86-16.txt	[x86] Fix 16-bit disassembly of JCXZ/JECXZ	2014-01-20 12:02:48 +00:00
x86-32.txt	Testcases for r224939.	2014-12-30 02:35:56 +00:00
x86-64.txt	[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.	2015-01-03 00:00:20 +00:00