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https://github.com/c64scene-ar/llvm-6502.git
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d950941e13
Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
1.2 KiB
LLVM
54 lines
1.2 KiB
LLVM
; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs | FileCheck %s
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; CHECK: .section .rodata
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; CHECK: JTI1_0:
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; CHECK: .long .BB1_1
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define i32 @oper(i32 %op, i32 %A, i32 %B) {
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entry:
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switch i32 %op, label %bbx [
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i32 1 , label %bb1
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i32 2 , label %bb2
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i32 3 , label %bb3
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i32 4 , label %bb4
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i32 5 , label %bb5
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i32 6 , label %bb6
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i32 7 , label %bb7
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i32 8 , label %bb8
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i32 9 , label %bb9
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i32 10, label %bb10
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]
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bb1:
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%R1 = add i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R1
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bb2:
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%R2 = sub i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R2
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bb3:
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%R3 = mul i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R3
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bb4:
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%R4 = sdiv i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R4
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bb5:
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%R5 = udiv i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R5
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bb6:
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%R6 = srem i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R6
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bb7:
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%R7 = urem i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R7
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bb8:
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%R8 = and i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R8
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bb9:
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%R9 = or i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R9
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bb10:
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%R10 = xor i32 %A, %B ; <i32> [#uses=1]
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ret i32 %R10
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bbx:
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ret i32 0
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}
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