llvm-6502/test/CodeGen/ARM64/addp.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

33 lines
915 B
LLVM

; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
define double @foo(<2 x double> %a) nounwind {
; CHECK-LABEL: foo:
; CHECK: faddp.2d d0, v0
; CHECK-NEXT: ret
%lane0.i = extractelement <2 x double> %a, i32 0
%lane1.i = extractelement <2 x double> %a, i32 1
%vpaddd.i = fadd double %lane0.i, %lane1.i
ret double %vpaddd.i
}
define i64 @foo0(<2 x i64> %a) nounwind {
; CHECK-LABEL: foo0:
; CHECK: addp.2d d0, v0
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
%lane0.i = extractelement <2 x i64> %a, i32 0
%lane1.i = extractelement <2 x i64> %a, i32 1
%vpaddd.i = add i64 %lane0.i, %lane1.i
ret i64 %vpaddd.i
}
define float @foo1(<2 x float> %a) nounwind {
; CHECK-LABEL: foo1:
; CHECK: faddp.2s
; CHECK-NEXT: ret
%lane0.i = extractelement <2 x float> %a, i32 0
%lane1.i = extractelement <2 x float> %a, i32 1
%vpaddd.i = fadd float %lane0.i, %lane1.i
ret float %vpaddd.i
}