llvm-6502/test/MC/ARM64/basic-a64-instructions.s
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

19 lines
918 B
ArmAsm

// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s
crc32b w5, w7, w20
crc32h w28, wzr, w30
crc32w w0, w1, w2
crc32x w7, w9, x20
crc32cb w9, w5, w4
crc32ch w13, w17, w25
crc32cw wzr, w3, w5
crc32cx w18, w16, xzr
// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a]
// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a]
// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a]
// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a]
// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a]
// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a]
// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a]