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with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
186 lines
6.0 KiB
C++
186 lines
6.0 KiB
C++
//===-- MBlazeISelLowering.h - MBlaze DAG Lowering Interface ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that MBlaze uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MBlazeISELLOWERING_H
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#define MBlazeISELLOWERING_H
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "MBlaze.h"
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#include "MBlazeSubtarget.h"
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namespace llvm {
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namespace MBlazeCC {
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enum CC {
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FIRST = 0,
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EQ,
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NE,
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GT,
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LT,
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GE,
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LE
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};
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inline static CC getOppositeCondition(CC cc) {
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switch (cc) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return NE;
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case NE: return EQ;
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case GT: return LE;
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case LT: return GE;
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case GE: return LT;
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case LE: return GE;
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}
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}
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inline static const char *MBlazeCCToString(CC cc) {
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switch (cc) {
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default: llvm_unreachable("Unknown condition code");
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case EQ: return "eq";
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case NE: return "ne";
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case GT: return "gt";
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case LT: return "lt";
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case GE: return "ge";
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case LE: return "le";
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}
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}
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}
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namespace MBlazeISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Jump and link (call)
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JmpLink,
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Select CC Pseudo Instruction
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Select_CC,
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// Wrap up multiple types of instructions
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Wrap,
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// Integer Compare
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ICmp,
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// Return from subroutine
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Ret,
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// Return from interrupt
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IRet
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MBlazeTargetLowering : public TargetLowering {
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public:
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explicit MBlazeTargetLowering(MBlazeTargetMachine &TM);
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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EVT getSetCCResultType(EVT VT) const;
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private:
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// Subtarget Info
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const MBlazeSubtarget *Subtarget;
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// Lower Operand helpers
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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// Lower Operand specifics
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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virtual MachineBasicBlock*
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EmitCustomShift(MachineInstr *MI, MachineBasicBlock *MBB) const;
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virtual MachineBasicBlock*
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EmitCustomSelect(MachineInstr *MI, MachineBasicBlock *MBB) const;
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virtual MachineBasicBlock*
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EmitCustomAtomic(MachineInstr *MI, MachineBasicBlock *MBB) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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};
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}
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#endif // MBlazeISELLOWERING_H
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