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259bda48e2
AggregateString += "\0\0"; Doesn't add two nuls to the AggregateString (for obvious reasons), which broke the asmprinter when the first character of an asm string was not literal text. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30625 91177308-0d34-0410-b5e6-96231b3b80d8
702 lines
25 KiB
C++
702 lines
25 KiB
C++
//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is emits an assembly printer for the current target.
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// Note that this is currently fairly skeletal, but will grow over time.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmWriterEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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#include <ostream>
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using namespace llvm;
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static bool isIdentChar(char C) {
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return (C >= 'a' && C <= 'z') ||
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(C >= 'A' && C <= 'Z') ||
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(C >= '0' && C <= '9') ||
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C == '_';
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}
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namespace {
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struct AsmWriterOperand {
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enum { isLiteralTextOperand, isMachineInstrOperand } OperandType;
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/// Str - For isLiteralTextOperand, this IS the literal text. For
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/// isMachineInstrOperand, this is the PrinterMethodName for the operand.
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std::string Str;
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/// MiOpNo - For isMachineInstrOperand, this is the operand number of the
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/// machine instruction.
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unsigned MIOpNo;
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/// MiModifier - For isMachineInstrOperand, this is the modifier string for
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/// an operand, specified with syntax like ${opname:modifier}.
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std::string MiModifier;
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AsmWriterOperand(const std::string &LitStr)
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: OperandType(isLiteralTextOperand), Str(LitStr) {}
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AsmWriterOperand(const std::string &Printer, unsigned OpNo,
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const std::string &Modifier)
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: OperandType(isMachineInstrOperand), Str(Printer), MIOpNo(OpNo),
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MiModifier(Modifier) {}
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bool operator!=(const AsmWriterOperand &Other) const {
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if (OperandType != Other.OperandType || Str != Other.Str) return true;
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if (OperandType == isMachineInstrOperand)
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return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier;
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return false;
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}
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bool operator==(const AsmWriterOperand &Other) const {
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return !operator!=(Other);
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}
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/// getCode - Return the code that prints this operand.
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std::string getCode() const;
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};
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}
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namespace llvm {
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struct AsmWriterInst {
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std::vector<AsmWriterOperand> Operands;
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const CodeGenInstruction *CGI;
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AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant);
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/// MatchesAllButOneOp - If this instruction is exactly identical to the
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/// specified instruction except for one differing operand, return the
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/// differing operand number. Otherwise return ~0.
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unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
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private:
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void AddLiteralString(const std::string &Str) {
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// If the last operand was already a literal text string, append this to
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// it, otherwise add a new operand.
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if (!Operands.empty() &&
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Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
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Operands.back().Str.append(Str);
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else
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Operands.push_back(AsmWriterOperand(Str));
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}
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};
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}
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std::string AsmWriterOperand::getCode() const {
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if (OperandType == isLiteralTextOperand)
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return "O << \"" + Str + "\"; ";
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std::string Result = Str + "(MI";
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if (MIOpNo != ~0U)
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Result += ", " + utostr(MIOpNo);
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if (!MiModifier.empty())
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Result += ", \"" + MiModifier + '"';
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return Result + "); ";
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}
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/// ParseAsmString - Parse the specified Instruction's AsmString into this
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/// AsmWriterInst.
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///
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AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned Variant) {
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this->CGI = &CGI;
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unsigned CurVariant = ~0U; // ~0 if we are outside a {.|.|.} region, other #.
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// NOTE: Any extensions to this code need to be mirrored in the
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// AsmPrinter::printInlineAsm code that executes as compile time (assuming
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// that inline asm strings should also get the new feature)!
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const std::string &AsmString = CGI.AsmString;
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std::string::size_type LastEmitted = 0;
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while (LastEmitted != AsmString.size()) {
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std::string::size_type DollarPos =
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AsmString.find_first_of("${|}", LastEmitted);
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if (DollarPos == std::string::npos) DollarPos = AsmString.size();
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// Emit a constant string fragment.
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if (DollarPos != LastEmitted) {
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// TODO: this should eventually handle escaping.
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if (CurVariant == Variant || CurVariant == ~0U)
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AddLiteralString(std::string(AsmString.begin()+LastEmitted,
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AsmString.begin()+DollarPos));
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LastEmitted = DollarPos;
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} else if (AsmString[DollarPos] == '{') {
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if (CurVariant != ~0U)
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throw "Nested variants found for instruction '" +
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CGI.TheDef->getName() + "'!";
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LastEmitted = DollarPos+1;
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CurVariant = 0; // We are now inside of the variant!
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} else if (AsmString[DollarPos] == '|') {
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if (CurVariant == ~0U)
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throw "'|' character found outside of a variant in instruction '"
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+ CGI.TheDef->getName() + "'!";
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++CurVariant;
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++LastEmitted;
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} else if (AsmString[DollarPos] == '}') {
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if (CurVariant == ~0U)
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throw "'}' character found outside of a variant in instruction '"
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+ CGI.TheDef->getName() + "'!";
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++LastEmitted;
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CurVariant = ~0U;
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} else if (DollarPos+1 != AsmString.size() &&
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AsmString[DollarPos+1] == '$') {
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if (CurVariant == Variant || CurVariant == ~0U)
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AddLiteralString("$"); // "$$" -> $
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LastEmitted = DollarPos+2;
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} else {
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// Get the name of the variable.
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std::string::size_type VarEnd = DollarPos+1;
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// handle ${foo}bar as $foo by detecting whether the character following
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// the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
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// so the variable name does not contain the leading curly brace.
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bool hasCurlyBraces = false;
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if (VarEnd < AsmString.size() && '{' == AsmString[VarEnd]) {
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hasCurlyBraces = true;
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++DollarPos;
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++VarEnd;
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}
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while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
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++VarEnd;
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std::string VarName(AsmString.begin()+DollarPos+1,
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AsmString.begin()+VarEnd);
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// Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
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// into printOperand. Also support ${:feature}, which is passed into
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// PrintSpecial.
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std::string Modifier;
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// In order to avoid starting the next string at the terminating curly
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// brace, advance the end position past it if we found an opening curly
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// brace.
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if (hasCurlyBraces) {
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if (VarEnd >= AsmString.size())
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throw "Reached end of string before terminating curly brace in '"
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+ CGI.TheDef->getName() + "'";
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// Look for a modifier string.
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if (AsmString[VarEnd] == ':') {
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++VarEnd;
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if (VarEnd >= AsmString.size())
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throw "Reached end of string before terminating curly brace in '"
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+ CGI.TheDef->getName() + "'";
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unsigned ModifierStart = VarEnd;
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while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
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++VarEnd;
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Modifier = std::string(AsmString.begin()+ModifierStart,
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AsmString.begin()+VarEnd);
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if (Modifier.empty())
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throw "Bad operand modifier name in '"+ CGI.TheDef->getName() + "'";
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}
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if (AsmString[VarEnd] != '}')
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throw "Variable name beginning with '{' did not end with '}' in '"
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+ CGI.TheDef->getName() + "'";
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++VarEnd;
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}
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if (VarName.empty() && Modifier.empty())
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throw "Stray '$' in '" + CGI.TheDef->getName() +
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"' asm string, maybe you want $$?";
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if (VarName.empty()) {
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// Just a modifier, pass this into PrintSpecial.
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Operands.push_back(AsmWriterOperand("PrintSpecial", ~0U, Modifier));
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} else {
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// Otherwise, normal operand.
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unsigned OpNo = CGI.getOperandNamed(VarName);
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CodeGenInstruction::OperandInfo OpInfo = CGI.OperandList[OpNo];
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// If this is a two-address instruction, verify the second operand isn't
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// used.
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unsigned MIOp = OpInfo.MIOperandNo;
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if (CGI.isTwoAddress && MIOp == 1)
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throw "Should refer to operand #0 instead of #1 for two-address"
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" instruction '" + CGI.TheDef->getName() + "'!";
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if (CurVariant == Variant || CurVariant == ~0U)
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Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, MIOp,
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Modifier));
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}
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LastEmitted = VarEnd;
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}
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}
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AddLiteralString("\\n");
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}
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/// MatchesAllButOneOp - If this instruction is exactly identical to the
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/// specified instruction except for one differing operand, return the differing
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/// operand number. If more than one operand mismatches, return ~1, otherwise
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/// if the instructions are identical return ~0.
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unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
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if (Operands.size() != Other.Operands.size()) return ~1;
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unsigned MismatchOperand = ~0U;
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for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
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if (Operands[i] != Other.Operands[i])
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if (MismatchOperand != ~0U) // Already have one mismatch?
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return ~1U;
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else
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MismatchOperand = i;
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}
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return MismatchOperand;
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}
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static void PrintCases(std::vector<std::pair<std::string,
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AsmWriterOperand> > &OpsToPrint, std::ostream &O) {
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O << " case " << OpsToPrint.back().first << ": ";
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AsmWriterOperand TheOp = OpsToPrint.back().second;
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OpsToPrint.pop_back();
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// Check to see if any other operands are identical in this list, and if so,
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// emit a case label for them.
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for (unsigned i = OpsToPrint.size(); i != 0; --i)
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if (OpsToPrint[i-1].second == TheOp) {
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O << "\n case " << OpsToPrint[i-1].first << ": ";
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OpsToPrint.erase(OpsToPrint.begin()+i-1);
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}
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// Finally, emit the code.
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O << TheOp.getCode();
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O << "break;\n";
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}
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/// EmitInstructions - Emit the last instruction in the vector and any other
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/// instructions that are suitably similar to it.
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static void EmitInstructions(std::vector<AsmWriterInst> &Insts,
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std::ostream &O) {
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AsmWriterInst FirstInst = Insts.back();
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Insts.pop_back();
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std::vector<AsmWriterInst> SimilarInsts;
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unsigned DifferingOperand = ~0;
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for (unsigned i = Insts.size(); i != 0; --i) {
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unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst);
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if (DiffOp != ~1U) {
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if (DifferingOperand == ~0U) // First match!
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DifferingOperand = DiffOp;
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// If this differs in the same operand as the rest of the instructions in
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// this class, move it to the SimilarInsts list.
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if (DifferingOperand == DiffOp || DiffOp == ~0U) {
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SimilarInsts.push_back(Insts[i-1]);
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Insts.erase(Insts.begin()+i-1);
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}
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}
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}
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O << " case " << FirstInst.CGI->Namespace << "::"
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<< FirstInst.CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i)
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O << " case " << SimilarInsts[i].CGI->Namespace << "::"
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<< SimilarInsts[i].CGI->TheDef->getName() << ":\n";
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for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) {
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if (i != DifferingOperand) {
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// If the operand is the same for all instructions, just print it.
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O << " " << FirstInst.Operands[i].getCode();
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} else {
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// If this is the operand that varies between all of the instructions,
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// emit a switch for just this operand now.
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O << " switch (MI->getOpcode()) {\n";
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std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint;
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OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" +
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FirstInst.CGI->TheDef->getName(),
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FirstInst.Operands[i]));
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for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) {
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AsmWriterInst &AWI = SimilarInsts[si];
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OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+
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AWI.CGI->TheDef->getName(),
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AWI.Operands[i]));
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}
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std::reverse(OpsToPrint.begin(), OpsToPrint.end());
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while (!OpsToPrint.empty())
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PrintCases(OpsToPrint, O);
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O << " }";
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}
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O << "\n";
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}
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O << " break;\n";
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}
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void AsmWriterEmitter::
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FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands,
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std::vector<unsigned> &InstIdxs,
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std::vector<unsigned> &InstOpsUsed) const {
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InstIdxs.assign(NumberedInstructions.size(), ~0U);
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// This vector parallels UniqueOperandCommands, keeping track of which
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// instructions each case are used for. It is a comma separated string of
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// enums.
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std::vector<std::string> InstrsForCase;
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InstrsForCase.resize(UniqueOperandCommands.size());
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InstOpsUsed.assign(UniqueOperandCommands.size(), 0);
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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const AsmWriterInst *Inst = getAsmWriterInstByID(i);
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if (Inst == 0) continue; // PHI, INLINEASM, etc.
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std::string Command;
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if (Inst->Operands.empty())
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continue; // Instruction already done.
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Command = " " + Inst->Operands[0].getCode() + "\n";
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// If this is the last operand, emit a return.
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if (Inst->Operands.size() == 1)
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Command += " return true;\n";
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// Check to see if we already have 'Command' in UniqueOperandCommands.
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// If not, add it.
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bool FoundIt = false;
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for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx)
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if (UniqueOperandCommands[idx] == Command) {
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InstIdxs[i] = idx;
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InstrsForCase[idx] += ", ";
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InstrsForCase[idx] += Inst->CGI->TheDef->getName();
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FoundIt = true;
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break;
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}
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if (!FoundIt) {
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InstIdxs[i] = UniqueOperandCommands.size();
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UniqueOperandCommands.push_back(Command);
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InstrsForCase.push_back(Inst->CGI->TheDef->getName());
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// This command matches one operand so far.
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InstOpsUsed.push_back(1);
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}
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}
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// For each entry of UniqueOperandCommands, there is a set of instructions
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// that uses it. If the next command of all instructions in the set are
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// identical, fold it into the command.
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for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size();
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CommandIdx != e; ++CommandIdx) {
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for (unsigned Op = 1; ; ++Op) {
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// Scan for the first instruction in the set.
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std::vector<unsigned>::iterator NIT =
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std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx);
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if (NIT == InstIdxs.end()) break; // No commonality.
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// If this instruction has no more operands, we isn't anything to merge
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// into this command.
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const AsmWriterInst *FirstInst =
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getAsmWriterInstByID(NIT-InstIdxs.begin());
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if (!FirstInst || FirstInst->Operands.size() == Op)
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break;
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// Otherwise, scan to see if all of the other instructions in this command
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// set share the operand.
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bool AllSame = true;
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for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
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NIT != InstIdxs.end();
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NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) {
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// Okay, found another instruction in this command set. If the operand
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// matches, we're ok, otherwise bail out.
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const AsmWriterInst *OtherInst =
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getAsmWriterInstByID(NIT-InstIdxs.begin());
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if (!OtherInst || OtherInst->Operands.size() == Op ||
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OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
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AllSame = false;
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break;
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}
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}
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if (!AllSame) break;
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// Okay, everything in this command set has the same next operand. Add it
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// to UniqueOperandCommands and remember that it was consumed.
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std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n";
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// If this is the last operand, emit a return after the code.
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if (FirstInst->Operands.size() == Op+1)
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Command += " return true;\n";
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UniqueOperandCommands[CommandIdx] += Command;
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InstOpsUsed[CommandIdx]++;
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}
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}
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// Prepend some of the instructions each case is used for onto the case val.
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for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) {
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std::string Instrs = InstrsForCase[i];
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if (Instrs.size() > 70) {
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Instrs.erase(Instrs.begin()+70, Instrs.end());
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Instrs += "...";
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}
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if (!Instrs.empty())
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UniqueOperandCommands[i] = " // " + Instrs + "\n" +
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UniqueOperandCommands[i];
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}
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}
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void AsmWriterEmitter::run(std::ostream &O) {
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EmitSourceFileHeader("Assembly Writer Source Fragment", O);
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CodeGenTarget Target;
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Record *AsmWriter = Target.getAsmWriter();
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std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
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unsigned Variant = AsmWriter->getValueAsInt("Variant");
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O <<
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"/// printInstruction - This method is automatically generated by tablegen\n"
|
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"/// from the instruction set description. This method returns true if the\n"
|
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"/// machine instruction was sufficiently described to print it, otherwise\n"
|
|
"/// it returns false.\n"
|
|
"bool " << Target.getName() << ClassName
|
|
<< "::printInstruction(const MachineInstr *MI) {\n";
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|
|
|
std::vector<AsmWriterInst> Instructions;
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|
|
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
|
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E = Target.inst_end(); I != E; ++I)
|
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if (!I->second.AsmString.empty())
|
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Instructions.push_back(AsmWriterInst(I->second, Variant));
|
|
|
|
// Get the instruction numbering.
|
|
Target.getInstructionsByEnumValue(NumberedInstructions);
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|
|
|
// Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not
|
|
// all machine instructions are necessarily being printed, so there may be
|
|
// target instructions not in this map.
|
|
for (unsigned i = 0, e = Instructions.size(); i != e; ++i)
|
|
CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i]));
|
|
|
|
// Build an aggregate string, and build a table of offsets into it.
|
|
std::map<std::string, unsigned> StringOffset;
|
|
std::string AggregateString;
|
|
AggregateString.push_back(0); // "\0"
|
|
AggregateString.push_back(0); // "\0"
|
|
|
|
/// OpcodeInfo - This encodes the index of the string to use for the first
|
|
/// chunk of the output as well as indices used for operand printing.
|
|
std::vector<unsigned> OpcodeInfo;
|
|
|
|
unsigned MaxStringIdx = 0;
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
|
|
unsigned Idx;
|
|
if (AWI == 0) {
|
|
// Something not handled by the asmwriter printer.
|
|
Idx = 0;
|
|
} else if (AWI->Operands[0].OperandType !=
|
|
AsmWriterOperand::isLiteralTextOperand ||
|
|
AWI->Operands[0].Str.empty()) {
|
|
// Something handled by the asmwriter printer, but with no leading string.
|
|
Idx = 1;
|
|
} else {
|
|
unsigned &Entry = StringOffset[AWI->Operands[0].Str];
|
|
if (Entry == 0) {
|
|
// Add the string to the aggregate if this is the first time found.
|
|
MaxStringIdx = Entry = AggregateString.size();
|
|
std::string Str = AWI->Operands[0].Str;
|
|
UnescapeString(Str);
|
|
AggregateString += Str;
|
|
AggregateString += '\0';
|
|
}
|
|
Idx = Entry;
|
|
|
|
// Nuke the string from the operand list. It is now handled!
|
|
AWI->Operands.erase(AWI->Operands.begin());
|
|
}
|
|
OpcodeInfo.push_back(Idx);
|
|
}
|
|
|
|
// Figure out how many bits we used for the string index.
|
|
unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx);
|
|
|
|
// To reduce code size, we compactify common instructions into a few bits
|
|
// in the opcode-indexed table.
|
|
unsigned BitsLeft = 32-AsmStrBits;
|
|
|
|
std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
|
|
|
|
bool isFirst = true;
|
|
while (1) {
|
|
std::vector<std::string> UniqueOperandCommands;
|
|
|
|
// For the first operand check, add a default value for instructions with
|
|
// just opcode strings to use.
|
|
if (isFirst) {
|
|
UniqueOperandCommands.push_back(" return true;\n");
|
|
isFirst = false;
|
|
}
|
|
|
|
std::vector<unsigned> InstIdxs;
|
|
std::vector<unsigned> NumInstOpsHandled;
|
|
FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs,
|
|
NumInstOpsHandled);
|
|
|
|
// If we ran out of operands to print, we're done.
|
|
if (UniqueOperandCommands.empty()) break;
|
|
|
|
// Compute the number of bits we need to represent these cases, this is
|
|
// ceil(log2(numentries)).
|
|
unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size());
|
|
|
|
// If we don't have enough bits for this operand, don't include it.
|
|
if (NumBits > BitsLeft) {
|
|
DEBUG(std::cerr << "Not enough bits to densely encode " << NumBits
|
|
<< " more bits\n");
|
|
break;
|
|
}
|
|
|
|
// Otherwise, we can include this in the initial lookup table. Add it in.
|
|
BitsLeft -= NumBits;
|
|
for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i)
|
|
if (InstIdxs[i] != ~0U)
|
|
OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits);
|
|
|
|
// Remove the info about this operand.
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
|
|
if (!Inst->Operands.empty()) {
|
|
unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
|
|
assert(NumOps <= Inst->Operands.size() &&
|
|
"Can't remove this many ops!");
|
|
Inst->Operands.erase(Inst->Operands.begin(),
|
|
Inst->Operands.begin()+NumOps);
|
|
}
|
|
}
|
|
|
|
// Remember the handlers for this set of operands.
|
|
TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
|
|
}
|
|
|
|
|
|
|
|
O<<" static const unsigned OpInfo[] = {\n";
|
|
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
|
|
O << " " << OpcodeInfo[i] << "U,\t// "
|
|
<< NumberedInstructions[i]->TheDef->getName() << "\n";
|
|
}
|
|
// Add a dummy entry so the array init doesn't end with a comma.
|
|
O << " 0U\n";
|
|
O << " };\n\n";
|
|
|
|
// Emit the string itself.
|
|
O << " const char *AsmStrs = \n \"";
|
|
unsigned CharsPrinted = 0;
|
|
EscapeString(AggregateString);
|
|
for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) {
|
|
if (CharsPrinted > 70) {
|
|
O << "\"\n \"";
|
|
CharsPrinted = 0;
|
|
}
|
|
O << AggregateString[i];
|
|
++CharsPrinted;
|
|
|
|
// Print escape sequences all together.
|
|
if (AggregateString[i] == '\\') {
|
|
assert(i+1 < AggregateString.size() && "Incomplete escape sequence!");
|
|
if (isdigit(AggregateString[i+1])) {
|
|
assert(isdigit(AggregateString[i+2]) && isdigit(AggregateString[i+3]) &&
|
|
"Expected 3 digit octal escape!");
|
|
O << AggregateString[++i];
|
|
O << AggregateString[++i];
|
|
O << AggregateString[++i];
|
|
CharsPrinted += 3;
|
|
} else {
|
|
O << AggregateString[++i];
|
|
++CharsPrinted;
|
|
}
|
|
}
|
|
}
|
|
O << "\";\n\n";
|
|
|
|
O << " if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {\n"
|
|
<< " printInlineAsm(MI);\n"
|
|
<< " return true;\n"
|
|
<< " }\n\n";
|
|
|
|
O << " // Emit the opcode for the instruction.\n"
|
|
<< " unsigned Bits = OpInfo[MI->getOpcode()];\n"
|
|
<< " if (Bits == 0) return false;\n"
|
|
<< " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ");\n\n";
|
|
|
|
// Output the table driven operand information.
|
|
BitsLeft = 32-AsmStrBits;
|
|
for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) {
|
|
std::vector<std::string> &Commands = TableDrivenOperandPrinters[i];
|
|
|
|
// Compute the number of bits we need to represent these cases, this is
|
|
// ceil(log2(numentries)).
|
|
unsigned NumBits = Log2_32_Ceil(Commands.size());
|
|
assert(NumBits <= BitsLeft && "consistency error");
|
|
|
|
// Emit code to extract this field from Bits.
|
|
BitsLeft -= NumBits;
|
|
|
|
O << "\n // Fragment " << i << " encoded into " << NumBits
|
|
<< " bits for " << Commands.size() << " unique commands.\n";
|
|
|
|
if (Commands.size() == 2) {
|
|
// Emit two possibilitys with if/else.
|
|
O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
<< Commands[1]
|
|
<< " } else {\n"
|
|
<< Commands[0]
|
|
<< " }\n\n";
|
|
} else {
|
|
O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & "
|
|
<< ((1 << NumBits)-1) << ") {\n"
|
|
<< " default: // unreachable.\n";
|
|
|
|
// Print out all the cases.
|
|
for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
|
|
O << " case " << i << ":\n";
|
|
O << Commands[i];
|
|
O << " break;\n";
|
|
}
|
|
O << " }\n\n";
|
|
}
|
|
}
|
|
|
|
// Okay, delete instructions with no operand info left.
|
|
for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
|
|
// Entire instruction has been emitted?
|
|
AsmWriterInst &Inst = Instructions[i];
|
|
if (Inst.Operands.empty()) {
|
|
Instructions.erase(Instructions.begin()+i);
|
|
--i; --e;
|
|
}
|
|
}
|
|
|
|
|
|
// Because this is a vector, we want to emit from the end. Reverse all of the
|
|
// elements in the vector.
|
|
std::reverse(Instructions.begin(), Instructions.end());
|
|
|
|
if (!Instructions.empty()) {
|
|
// Find the opcode # of inline asm.
|
|
O << " switch (MI->getOpcode()) {\n";
|
|
while (!Instructions.empty())
|
|
EmitInstructions(Instructions, O);
|
|
|
|
O << " }\n";
|
|
O << " return true;\n";
|
|
}
|
|
|
|
O << "}\n";
|
|
}
|