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https://github.com/c64scene-ar/llvm-6502.git
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5e00954197
GPR and FPR constraints like "{r2}" and "{f2}" weren't handled correctly
because the name-to-regno mapping depends on the value type and
(because of that) the internal names in RegStrings are not the
same as the AsmName.
CC constraints like "{cc}" didn't work either because there was no
associated register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186148 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
3.8 KiB
C++
109 lines
3.8 KiB
C++
//===-- SystemZMCInstLower.cpp - Lower MachineInstr to MCInst -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZMCInstLower.h"
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#include "SystemZAsmPrinter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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// If Opcode is an interprocedural reference that can be shortened,
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// return the short form, otherwise return 0.
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static unsigned getShortenedInstr(unsigned Opcode) {
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switch (Opcode) {
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case SystemZ::BRASL: return SystemZ::BRAS;
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}
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return Opcode;
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}
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// Return the VK_* enumeration for MachineOperand target flags Flags.
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static MCSymbolRefExpr::VariantKind getVariantKind(unsigned Flags) {
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switch (Flags & SystemZII::MO_SYMBOL_MODIFIER) {
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case 0:
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return MCSymbolRefExpr::VK_None;
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case SystemZII::MO_GOT:
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return MCSymbolRefExpr::VK_GOT;
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}
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llvm_unreachable("Unrecognised MO_ACCESS_MODEL");
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}
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SystemZMCInstLower::SystemZMCInstLower(Mangler *mang, MCContext &ctx,
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SystemZAsmPrinter &asmprinter)
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: Mang(mang), Ctx(ctx), AsmPrinter(asmprinter) {}
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MCOperand SystemZMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
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const MCSymbol *Symbol,
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int64_t Offset) const {
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MCSymbolRefExpr::VariantKind Kind = getVariantKind(MO.getTargetFlags());
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const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, Kind, Ctx);
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if (Offset) {
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const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
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Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
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}
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return MCOperand::CreateExpr(Expr);
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}
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MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
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switch (MO.getType()) {
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default:
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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return MCOperand::CreateReg(MO.getReg());
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case MachineOperand::MO_Immediate:
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return MCOperand::CreateImm(MO.getImm());
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case MachineOperand::MO_MachineBasicBlock:
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return lowerSymbolOperand(MO, MO.getMBB()->getSymbol(),
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/* MO has no offset field */0);
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case MachineOperand::MO_GlobalAddress:
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return lowerSymbolOperand(MO, Mang->getSymbol(MO.getGlobal()),
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MO.getOffset());
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case MachineOperand::MO_ExternalSymbol: {
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StringRef Name = MO.getSymbolName();
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return lowerSymbolOperand(MO, AsmPrinter.GetExternalSymbolSymbol(Name),
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MO.getOffset());
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}
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case MachineOperand::MO_JumpTableIndex:
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return lowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()),
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/* MO has no offset field */0);
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case MachineOperand::MO_ConstantPoolIndex:
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return lowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()),
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MO.getOffset());
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case MachineOperand::MO_BlockAddress: {
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const BlockAddress *BA = MO.getBlockAddress();
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return lowerSymbolOperand(MO, AsmPrinter.GetBlockAddressSymbol(BA),
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MO.getOffset());
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}
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}
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}
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void SystemZMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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unsigned Opcode = MI->getOpcode();
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// When emitting binary code, start with the shortest form of an instruction
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// and then relax it where necessary.
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if (!AsmPrinter.OutStreamer.hasRawTextSupport())
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Opcode = getShortenedInstr(Opcode);
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OutMI.setOpcode(Opcode);
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for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
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const MachineOperand &MO = MI->getOperand(I);
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// Ignore all implicit register operands.
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if (!MO.isReg() || !MO.isImplicit())
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OutMI.addOperand(lowerOperand(MO));
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}
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}
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