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6b50a7d179
With optimizations disabled, we disable the isel patterns for mul.wide; but we were still generating MULWIDE ISD nodes. Now, we only try to generate MULWIDE ISD nodes in DAGCombine if the optimization level is not zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213773 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.1 KiB
LLVM
47 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O3 | FileCheck %s --check-prefix=OPT
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O0 | FileCheck %s --check-prefix=NOOPT
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; OPT-LABEL: @mulwide16
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; NOOPT-LABEL: @mulwide16
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define i32 @mulwide16(i16 %a, i16 %b) {
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; OPT: mul.wide.s16
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; NOOPT: mul.lo.s32
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%val0 = sext i16 %a to i32
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%val1 = sext i16 %b to i32
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%val2 = mul i32 %val0, %val1
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ret i32 %val2
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}
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; OPT-LABEL: @mulwideu16
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; NOOPT-LABEL: @mulwideu16
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define i32 @mulwideu16(i16 %a, i16 %b) {
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; OPT: mul.wide.u16
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; NOOPT: mul.lo.s32
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%val0 = zext i16 %a to i32
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%val1 = zext i16 %b to i32
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%val2 = mul i32 %val0, %val1
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ret i32 %val2
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}
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; OPT-LABEL: @mulwide32
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; NOOPT-LABEL: @mulwide32
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define i64 @mulwide32(i32 %a, i32 %b) {
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; OPT: mul.wide.s32
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; NOOPT: mul.lo.s64
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%val0 = sext i32 %a to i64
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%val1 = sext i32 %b to i64
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%val2 = mul i64 %val0, %val1
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ret i64 %val2
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}
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; OPT-LABEL: @mulwideu32
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; NOOPT-LABEL: @mulwideu32
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define i64 @mulwideu32(i32 %a, i32 %b) {
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; OPT: mul.wide.u32
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; NOOPT: mul.lo.s64
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%val0 = zext i32 %a to i64
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%val1 = zext i32 %b to i64
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%val2 = mul i64 %val0, %val1
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ret i64 %val2
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}
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