mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-19 01:34:32 +00:00
9568e5c3c3
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
1.2 KiB
LLVM
60 lines
1.2 KiB
LLVM
; bswap should be constant folded when it is passed a constant argument
|
|
|
|
; RUN: llc < %s -march=x86 | FileCheck %s
|
|
|
|
declare i16 @llvm.bswap.i16(i16)
|
|
|
|
declare i32 @llvm.bswap.i32(i32)
|
|
|
|
declare i64 @llvm.bswap.i64(i64)
|
|
|
|
define i16 @W(i16 %A) {
|
|
; CHECK: W:
|
|
; CHECK: rolw $8, %ax
|
|
%Z = call i16 @llvm.bswap.i16( i16 %A ) ; <i16> [#uses=1]
|
|
ret i16 %Z
|
|
}
|
|
|
|
define i32 @X(i32 %A) {
|
|
; CHECK: X:
|
|
; CHECK: bswapl %eax
|
|
%Z = call i32 @llvm.bswap.i32( i32 %A ) ; <i32> [#uses=1]
|
|
ret i32 %Z
|
|
}
|
|
|
|
define i64 @Y(i64 %A) {
|
|
; CHECK: Y:
|
|
; CHECK: bswapl %eax
|
|
; CHECK: bswapl %edx
|
|
%Z = call i64 @llvm.bswap.i64( i64 %A ) ; <i64> [#uses=1]
|
|
ret i64 %Z
|
|
}
|
|
|
|
; rdar://9164521
|
|
define i32 @test1(i32 %a) nounwind readnone {
|
|
entry:
|
|
; CHECK: test1
|
|
; CHECK: bswapl %eax
|
|
; CHECK: shrl $16, %eax
|
|
%and = lshr i32 %a, 8
|
|
%shr3 = and i32 %and, 255
|
|
%and2 = shl i32 %a, 8
|
|
%shl = and i32 %and2, 65280
|
|
%or = or i32 %shr3, %shl
|
|
ret i32 %or
|
|
}
|
|
|
|
define i32 @test2(i32 %a) nounwind readnone {
|
|
entry:
|
|
; CHECK: test2
|
|
; CHECK: bswapl %eax
|
|
; CHECK: sarl $16, %eax
|
|
%and = lshr i32 %a, 8
|
|
%shr4 = and i32 %and, 255
|
|
%and2 = shl i32 %a, 8
|
|
%or = or i32 %shr4, %and2
|
|
%sext = shl i32 %or, 16
|
|
%conv3 = ashr exact i32 %sext, 16
|
|
ret i32 %conv3
|
|
}
|