mirror of
https://github.com/c64scene-ar/llvm-6502.git
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into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
724 lines
26 KiB
C++
724 lines
26 KiB
C++
//===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1RegisterInfo.h"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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extern cl::opt<bool> ReuseFrameIndexVals;
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}
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using namespace llvm;
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Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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: ARMBaseRegisterInfo(tii, sti) {
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}
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const TargetRegisterClass*
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Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
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const {
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if (ARM::tGPRRegClass.hasSubClassEq(RC))
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return &ARM::tGPRRegClass;
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return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
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}
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const TargetRegisterClass *
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Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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return &ARM::tGPRRegClass;
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void
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Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) const {
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MachineFunction &MF = *MBB.getParent();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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const Constant *C = ConstantInt::get(
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Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
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.addReg(DestReg, getDefRegState(true), SubIdx)
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.addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
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.setMIFlags(MIFlags);
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}
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/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
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/// in a register using mov / mvn sequences or load the immediate from a
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/// constpool entry.
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static
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void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, bool CanChangeCC,
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const TargetInstrInfo &TII,
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const ARMBaseRegisterInfo& MRI,
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unsigned MIFlags = MachineInstr::NoFlags) {
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MachineFunction &MF = *MBB.getParent();
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bool isHigh = !isARMLowRegister(DestReg) ||
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(BaseReg != 0 && !isARMLowRegister(BaseReg));
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bool isSub = false;
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// Subtract doesn't have high register version. Load the negative value
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// if either base or dest register is a high register. Also, if do not
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// issue sub as part of the sequence if condition register is to be
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// preserved.
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if (NumBytes < 0 && !isHigh && CanChangeCC) {
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isSub = true;
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NumBytes = -NumBytes;
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}
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unsigned LdReg = DestReg;
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if (DestReg == ARM::SP) {
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assert(BaseReg == ARM::SP && "Unexpected!");
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LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
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}
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if (NumBytes <= 255 && NumBytes >= 0)
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
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.addImm(NumBytes).setMIFlags(MIFlags);
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else if (NumBytes < 0 && NumBytes >= -255) {
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
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.addImm(NumBytes).setMIFlags(MIFlags);
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
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.addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
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} else
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MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes,
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ARMCC::AL, 0, MIFlags);
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// Emit add / sub.
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int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (Opc != ARM::tADDhirr)
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MIB = AddDefaultT1CC(MIB);
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if (DestReg == ARM::SP || isSub)
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MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
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else
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MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
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AddDefaultPred(MIB);
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}
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/// calcNumMI - Returns the number of instructions required to materialize
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/// the specific add / sub r, c instruction.
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static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
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unsigned NumBits, unsigned Scale) {
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unsigned NumMIs = 0;
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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if (Opc == ARM::tADDrSPi) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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NumMIs++;
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NumBits = 8;
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Scale = 1; // Followed by a number of tADDi8.
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Chunk = ((1 << NumBits) - 1) * Scale;
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}
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NumMIs += Bytes / Chunk;
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if ((Bytes % Chunk) != 0)
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NumMIs++;
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if (ExtraOpc)
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NumMIs++;
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return NumMIs;
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}
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/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code.
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void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned BaseReg,
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int NumBytes, const TargetInstrInfo &TII,
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const ARMBaseRegisterInfo& MRI,
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unsigned MIFlags) {
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bool isSub = NumBytes < 0;
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unsigned Bytes = (unsigned)NumBytes;
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if (isSub) Bytes = -NumBytes;
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bool isMul4 = (Bytes & 3) == 0;
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bool isTwoAddr = false;
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bool DstNotEqBase = false;
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unsigned NumBits = 1;
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unsigned Scale = 1;
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int Opc = 0;
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int ExtraOpc = 0;
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bool NeedCC = false;
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if (DestReg == BaseReg && BaseReg == ARM::SP) {
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assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
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NumBits = 7;
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Scale = 4;
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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isTwoAddr = true;
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} else if (!isSub && BaseReg == ARM::SP) {
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// r1 = add sp, 403
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// =>
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// r1 = add sp, 100 * 4
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// r1 = add r1, 3
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if (!isMul4) {
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Bytes &= ~3;
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ExtraOpc = ARM::tADDi3;
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}
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NumBits = 8;
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Scale = 4;
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Opc = ARM::tADDrSPi;
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} else {
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// sp = sub sp, c
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// r1 = sub sp, c
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// r8 = sub sp, c
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if (DestReg != BaseReg)
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DstNotEqBase = true;
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NumBits = 8;
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if (DestReg == ARM::SP) {
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
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NumBits = 7;
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Scale = 4;
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} else {
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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NumBits = 8;
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NeedCC = true;
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}
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isTwoAddr = true;
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}
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unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
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unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
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if (NumMIs > Threshold) {
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// This will expand into too many instructions. Load the immediate from a
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// constpool entry.
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emitThumbRegPlusImmInReg(MBB, MBBI, dl,
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DestReg, BaseReg, NumBytes, true,
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TII, MRI, MIFlags);
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return;
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}
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if (DstNotEqBase) {
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if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
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// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
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unsigned Chunk = (1 << 3) - 1;
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
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const MachineInstrBuilder MIB =
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
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.setMIFlags(MIFlags));
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AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
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} else {
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
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.addReg(BaseReg, RegState::Kill))
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.setMIFlags(MIFlags);
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}
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BaseReg = DestReg;
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}
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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while (Bytes) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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ThisVal /= Scale;
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// Build the new tADD / tSUB.
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if (isTwoAddr) {
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (NeedCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(DestReg).addImm(ThisVal);
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MIB = AddDefaultPred(MIB);
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MIB.setMIFlags(MIFlags);
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} else {
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bool isKill = BaseReg != ARM::SP;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (NeedCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
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MIB = AddDefaultPred(MIB);
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MIB.setMIFlags(MIFlags);
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BaseReg = DestReg;
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if (Opc == ARM::tADDrSPi) {
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// r4 = add sp, imm
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// r4 = add r4, imm
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// ...
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NumBits = 8;
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Scale = 1;
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Chunk = ((1 << NumBits) - 1) * Scale;
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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NeedCC = isTwoAddr = true;
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}
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}
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}
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if (ExtraOpc) {
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const MCInstrDesc &MCID = TII.get(ExtraOpc);
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AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
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.addReg(DestReg, RegState::Kill)
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.addImm(((unsigned)NumBytes) & 3)
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.setMIFlags(MIFlags));
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}
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}
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static void emitSPUpdate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetInstrInfo &TII, DebugLoc dl,
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const Thumb1RegisterInfo &MRI,
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int NumBytes) {
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emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
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MRI);
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}
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void Thumb1RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (!TFI->hasReservedCallFrame(MF)) {
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// If we have alloca, convert as follows:
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// ADJCALLSTACKDOWN -> sub, sp, sp, amount
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// ADJCALLSTACKUP -> add, sp, sp, amount
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MachineInstr *Old = I;
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DebugLoc dl = Old->getDebugLoc();
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unsigned Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = TFI->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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unsigned Opc = Old->getOpcode();
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if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
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emitSPUpdate(MBB, I, TII, dl, *this, -Amount);
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} else {
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assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
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emitSPUpdate(MBB, I, TII, dl, *this, Amount);
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}
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}
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}
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MBB.erase(I);
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}
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/// emitThumbConstant - Emit a series of instructions to materialize a
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/// constant.
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static void emitThumbConstant(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, int Imm,
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const TargetInstrInfo &TII,
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const Thumb1RegisterInfo& MRI,
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DebugLoc dl) {
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bool isSub = Imm < 0;
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if (isSub) Imm = -Imm;
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int Chunk = (1 << 8) - 1;
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int ThisVal = (Imm > Chunk) ? Chunk : Imm;
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Imm -= ThisVal;
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AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
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DestReg))
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.addImm(ThisVal));
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if (Imm > 0)
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emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI);
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if (isSub) {
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const MCInstrDesc &MCID = TII.get(ARM::tRSB);
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AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
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.addReg(DestReg, RegState::Kill));
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}
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}
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static void removeOperands(MachineInstr &MI, unsigned i) {
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unsigned Op = i;
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for (unsigned e = MI.getNumOperands(); i != e; ++i)
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MI.RemoveOperand(Op);
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}
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/// convertToNonSPOpcode - Change the opcode to the non-SP version, because
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/// we're replacing the frame index with a non-SP register.
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static unsigned convertToNonSPOpcode(unsigned Opcode) {
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switch (Opcode) {
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case ARM::tLDRspi:
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return ARM::tLDRi;
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case ARM::tSTRspi:
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return ARM::tSTRi;
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}
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return Opcode;
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}
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bool Thumb1RegisterInfo::
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rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) const {
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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MachineInstrBuilder MIB(*MBB.getParent(), &MI);
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unsigned Opcode = MI.getOpcode();
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const MCInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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if (Opcode == ARM::tADDrSPi) {
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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// Can't use tADDrSPi if it's based off the frame pointer.
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unsigned NumBits = 0;
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unsigned Scale = 1;
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if (FrameReg != ARM::SP) {
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Opcode = ARM::tADDi3;
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NumBits = 3;
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} else {
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NumBits = 8;
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Scale = 4;
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assert((Offset & 3) == 0 &&
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"Thumb add/sub sp, #imm immediate must be multiple of 4!");
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}
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unsigned PredReg;
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if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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// Turn it into a move.
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MI.setDesc(TII.get(ARM::tMOVr));
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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// Remove offset
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MI.RemoveOperand(FrameRegIdx+1);
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return true;
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}
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// Common case: small offset, fits into instruction.
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unsigned Mask = (1 << NumBits) - 1;
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if (((Offset / Scale) & ~Mask) == 0) {
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// Replace the FrameIndex with sp / fp
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if (Opcode == ARM::tADDi3) {
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MI.setDesc(TII.get(Opcode));
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removeOperands(MI, FrameRegIdx);
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AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
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.addImm(Offset / Scale));
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} else {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset / Scale);
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}
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return true;
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}
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned Bytes = (Offset > 0) ? Offset : -Offset;
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unsigned NumMIs = calcNumMI(Opcode, 0, Bytes, NumBits, Scale);
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// MI would expand into a large number of instructions. Don't try to
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// simplify the immediate.
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if (NumMIs > 2) {
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emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
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*this);
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MBB.erase(II);
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return true;
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}
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if (Offset > 0) {
|
|
// Translate r0 = add sp, imm to
|
|
// r0 = add sp, 255*4
|
|
// r0 = add r0, (imm - 255*4)
|
|
if (Opcode == ARM::tADDi3) {
|
|
MI.setDesc(TII.get(Opcode));
|
|
removeOperands(MI, FrameRegIdx);
|
|
AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
|
|
} else {
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Mask);
|
|
}
|
|
Offset = (Offset - Mask * Scale);
|
|
MachineBasicBlock::iterator NII = llvm::next(II);
|
|
emitThumbRegPlusImmediate(MBB, NII, dl, DestReg, DestReg, Offset, TII,
|
|
*this);
|
|
} else {
|
|
// Translate r0 = add sp, -imm to
|
|
// r0 = -imm (this is then translated into a series of instructons)
|
|
// r0 = add r0, sp
|
|
emitThumbConstant(MBB, II, DestReg, Offset, TII, *this, dl);
|
|
|
|
MI.setDesc(TII.get(ARM::tADDhirr));
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(DestReg, false, false, true);
|
|
MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
|
|
}
|
|
return true;
|
|
} else {
|
|
if (AddrMode != ARMII::AddrModeT1_s)
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
|
|
unsigned ImmIdx = FrameRegIdx + 1;
|
|
int InstrOffs = MI.getOperand(ImmIdx).getImm();
|
|
unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
|
|
unsigned Scale = 4;
|
|
|
|
Offset += InstrOffs * Scale;
|
|
assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
|
|
|
|
// Common case: small offset, fits into instruction.
|
|
MachineOperand &ImmOp = MI.getOperand(ImmIdx);
|
|
int ImmedOffset = Offset / Scale;
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
|
|
if ((unsigned)Offset <= Mask * Scale) {
|
|
// Replace the FrameIndex with the frame register (e.g., sp).
|
|
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
|
|
// If we're using a register where sp was stored, convert the instruction
|
|
// to the non-SP version.
|
|
unsigned NewOpc = convertToNonSPOpcode(Opcode);
|
|
if (NewOpc != Opcode && FrameReg != ARM::SP)
|
|
MI.setDesc(TII.get(NewOpc));
|
|
|
|
return true;
|
|
}
|
|
|
|
NumBits = 5;
|
|
Mask = (1 << NumBits) - 1;
|
|
|
|
// If this is a thumb spill / restore, we will be using a constpool load to
|
|
// materialize the offset.
|
|
if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
|
|
ImmOp.ChangeToImmediate(0);
|
|
} else {
|
|
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
|
|
ImmedOffset = ImmedOffset & Mask;
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
Offset &= ~(Mask * Scale);
|
|
}
|
|
}
|
|
|
|
return Offset == 0;
|
|
}
|
|
|
|
void
|
|
Thumb1RegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
unsigned BaseReg, int64_t Offset) const {
|
|
MachineInstr &MI = *I;
|
|
int Off = Offset; // ARM doesn't need the general 64-bit offsets
|
|
unsigned i = 0;
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
|
|
assert (Done && "Unable to resolve frame index!");
|
|
(void)Done;
|
|
}
|
|
|
|
/// saveScavengerRegister - Spill the register so it can be used by the
|
|
/// register scavenger. Return true.
|
|
bool
|
|
Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
MachineBasicBlock::iterator &UseMI,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Reg) const {
|
|
// Thumb1 can't use the emergency spill slot on the stack because
|
|
// ldr/str immediate offsets must be positive, and if we're referencing
|
|
// off the frame pointer (if, for example, there are alloca() calls in
|
|
// the function, the offset will be negative. Use R12 instead since that's
|
|
// a call clobbered register that we know won't be used in Thumb1 mode.
|
|
DebugLoc DL;
|
|
AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
|
|
.addReg(ARM::R12, RegState::Define)
|
|
.addReg(Reg, RegState::Kill));
|
|
|
|
// The UseMI is where we would like to restore the register. If there's
|
|
// interference with R12 before then, however, we'll need to restore it
|
|
// before that instead and adjust the UseMI.
|
|
bool done = false;
|
|
for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
|
|
if (II->isDebugValue())
|
|
continue;
|
|
// If this instruction affects R12, adjust our restore point.
|
|
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = II->getOperand(i);
|
|
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) {
|
|
UseMI = II;
|
|
done = true;
|
|
break;
|
|
}
|
|
if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
|
|
TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
|
continue;
|
|
if (MO.getReg() == ARM::R12) {
|
|
UseMI = II;
|
|
done = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
// Restore the register from R12
|
|
AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
|
|
addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
|
|
|
|
return true;
|
|
}
|
|
|
|
void
|
|
Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const {
|
|
unsigned VReg = 0;
|
|
unsigned i = 0;
|
|
MachineInstr &MI = *II;
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
MachineInstrBuilder MIB(*MBB.getParent(), &MI);
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
unsigned FrameReg = ARM::SP;
|
|
int FrameIndex = MI.getOperand(i).getIndex();
|
|
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
|
|
MF.getFrameInfo()->getStackSize() + SPAdj;
|
|
|
|
if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
|
|
Offset -= AFI->getGPRCalleeSavedArea1Offset();
|
|
else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
|
|
Offset -= AFI->getGPRCalleeSavedArea2Offset();
|
|
else if (MF.getFrameInfo()->hasVarSizedObjects()) {
|
|
assert(SPAdj == 0 && MF.getTarget().getFrameLowering()->hasFP(MF) &&
|
|
"Unexpected");
|
|
// There are alloca()'s in this function, must reference off the frame
|
|
// pointer or base pointer instead.
|
|
if (!hasBasePointer(MF)) {
|
|
FrameReg = getFrameRegister(MF);
|
|
Offset -= AFI->getFramePtrSpillOffset();
|
|
} else
|
|
FrameReg = BasePtr;
|
|
}
|
|
|
|
// PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
|
|
// call frame setup/destroy instructions have already been eliminated. That
|
|
// means the stack pointer cannot be used to access the emergency spill slot
|
|
// when !hasReservedCallFrame().
|
|
#ifndef NDEBUG
|
|
if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
|
|
assert(MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF) &&
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
"functions without a reserved call frame");
|
|
assert(!MF.getFrameInfo()->hasVarSizedObjects() &&
|
|
"Cannot use SP to access the emergency spill slot in "
|
|
"functions with variable sized frame objects");
|
|
}
|
|
#endif // NDEBUG
|
|
|
|
// Special handling of dbg_value instructions.
|
|
if (MI.isDebugValue()) {
|
|
MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
|
|
MI.getOperand(i+1).ChangeToImmediate(Offset);
|
|
return;
|
|
}
|
|
|
|
// Modify MI as necessary to handle as much of 'Offset' as possible
|
|
assert(AFI->isThumbFunction() &&
|
|
"This eliminateFrameIndex only supports Thumb1!");
|
|
if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
|
|
return;
|
|
|
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
// as much as possible above, handle the rest, providing a register that is
|
|
// SP+LargeImm.
|
|
assert(Offset && "This code isn't needed if offset already handled!");
|
|
|
|
unsigned Opcode = MI.getOpcode();
|
|
|
|
// Remove predicate first.
|
|
int PIdx = MI.findFirstPredOperandIdx();
|
|
if (PIdx != -1)
|
|
removeOperands(MI, PIdx);
|
|
|
|
if (MI.mayLoad()) {
|
|
// Use the destination register to materialize sp + offset.
|
|
unsigned TmpReg = MI.getOperand(0).getReg();
|
|
bool UseRR = false;
|
|
if (Opcode == ARM::tLDRspi) {
|
|
if (FrameReg == ARM::SP)
|
|
emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
|
|
Offset, false, TII, *this);
|
|
else {
|
|
emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
|
|
UseRR = true;
|
|
}
|
|
} else {
|
|
emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
|
|
*this);
|
|
}
|
|
|
|
MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
|
|
MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
|
|
if (UseRR)
|
|
// Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
|
// register. The offset is already handled in the vreg value.
|
|
MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
|
|
} else if (MI.mayStore()) {
|
|
VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
|
|
bool UseRR = false;
|
|
|
|
if (Opcode == ARM::tSTRspi) {
|
|
if (FrameReg == ARM::SP)
|
|
emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
|
|
Offset, false, TII, *this);
|
|
else {
|
|
emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
|
|
UseRR = true;
|
|
}
|
|
} else
|
|
emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
|
|
*this);
|
|
MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
|
|
MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
|
|
if (UseRR)
|
|
// Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
|
|
// register. The offset is already handled in the vreg value.
|
|
MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
|
|
} else {
|
|
llvm_unreachable("Unexpected opcode!");
|
|
}
|
|
|
|
// Add predicate back if it's needed.
|
|
if (MI.isPredicable())
|
|
AddDefaultPred(MIB);
|
|
}
|