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With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack. The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74764 91177308-0d34-0410-b5e6-96231b3b80d8
633 lines
24 KiB
C++
633 lines
24 KiB
C++
//===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the IA64ISelLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "IA64ISelLowering.h"
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#include "IA64MachineFunctionInfo.h"
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#include "IA64TargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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using namespace llvm;
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IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// register class for general registers
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addRegisterClass(MVT::i64, IA64::GRRegisterClass);
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// register class for FP registers
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addRegisterClass(MVT::f64, IA64::FPRegisterClass);
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// register class for predicate registers
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addRegisterClass(MVT::i1, IA64::PRRegisterClass);
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setLoadExtAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setLoadExtAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
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setLoadExtAction(ISD::SEXTLOAD , MVT::i1 , Promote);
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setLoadExtAction(ISD::SEXTLOAD , MVT::i8 , Expand);
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setLoadExtAction(ISD::SEXTLOAD , MVT::i16 , Expand);
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setLoadExtAction(ISD::SEXTLOAD , MVT::i32 , Expand);
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setOperationAction(ISD::BRIND , MVT::Other, Expand);
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setOperationAction(ISD::BR_JT , MVT::Other, Expand);
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setOperationAction(ISD::BR_CC , MVT::Other, Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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// ia64 uses SELECT not SELECT_CC
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setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
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// We need to handle ISD::RET for void functions ourselves,
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// so we get a chance to restore ar.pfs before adding a
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// br.ret insn
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setShiftAmountType(MVT::i64);
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setOperationAction(ISD::FREM , MVT::f32 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::UREM , MVT::f32 , Expand);
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setOperationAction(ISD::UREM , MVT::f64 , Expand);
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
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// We don't support sin/cos/sqrt/pow
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FPOW , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::FPOW , MVT::f32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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// FIXME: IA64 supports fcopysign natively!
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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// IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer
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// expansion for ctlz/cttz in terms of ctpop is much larger, but lower
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// latency.
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// FIXME: Custom lower CTLZ when compiling for size?
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::ROTL , MVT::i64 , Expand);
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setOperationAction(ISD::ROTR , MVT::i64 , Expand);
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// FIXME: IA64 has this, but is not implemented. should be mux @rev
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setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
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// VASTART needs to be custom lowered to use the VarArgsFrameIndex
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setOperationAction(ISD::VAARG , MVT::Other, Custom);
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setOperationAction(ISD::VASTART , MVT::Other, Custom);
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// FIXME: These should be legal
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setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
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setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
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// Use the default implementation.
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setOperationAction(ISD::VACOPY , MVT::Other, Expand);
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setOperationAction(ISD::VAEND , MVT::Other, Expand);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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// Thread Local Storage
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setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
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setStackPointerRegisterToSaveRestore(IA64::r12);
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setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
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setJumpBufAlignment(16); // ...and must be 16-byte aligned
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computeRegisterProperties();
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addLegalFPImmediate(APFloat(+0.0));
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addLegalFPImmediate(APFloat(-0.0));
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addLegalFPImmediate(APFloat(+1.0));
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addLegalFPImmediate(APFloat(-1.0));
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}
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const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case IA64ISD::GETFD: return "IA64ISD::GETFD";
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case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
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case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
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}
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}
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MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
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return MVT::i1;
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}
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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unsigned IA64TargetLowering::getFunctionAlignment(const Function *) const {
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return 5;
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}
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void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &ArgValues,
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DebugLoc dl) {
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//
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// add beautiful description of IA64 stack frame format
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// here (from intel 24535803.pdf most likely)
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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MachineBasicBlock& BB = MF.front();
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unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
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IA64::r36, IA64::r37, IA64::r38, IA64::r39};
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unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
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IA64::F12,IA64::F13,IA64::F14, IA64::F15};
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unsigned argVreg[8];
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unsigned argPreg[8];
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unsigned argOpc[8];
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unsigned used_FPArgs = 0; // how many FP args have been used so far?
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unsigned ArgOffset = 0;
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int count = 0;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
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{
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SDValue newroot, argt;
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if(count < 8) { // need to fix this logic? maybe.
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switch (getValueType(I->getType()).getSimpleVT()) {
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default:
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assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
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case MVT::f32:
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// fixme? (well, will need to for weird FP structy stuff,
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// see intel ABI docs)
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case MVT::f64:
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//XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
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MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
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// mark this reg as liveIn
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// floating point args go into f8..f15 as-needed, the increment
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argVreg[count] = // is below..:
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MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
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// FP args go into f8..f15 as needed: (hence the ++)
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argPreg[count] = args_FP[used_FPArgs++];
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argOpc[count] = IA64::FMOV;
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl,
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argVreg[count], MVT::f64);
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if (I->getType() == Type::FloatTy)
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argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
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DAG.getIntPtrConstant(0));
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break;
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case MVT::i1: // NOTE: as far as C abi stuff goes,
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// bools are just boring old ints
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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//XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
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MF.getRegInfo().addLiveIn(args_int[count]);
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// mark this register as liveIn
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argVreg[count] =
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MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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argPreg[count] = args_int[count];
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argOpc[count] = IA64::MOV;
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argt = newroot =
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DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64);
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if ( getValueType(I->getType()) != MVT::i64)
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argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
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newroot);
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break;
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}
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} else { // more than 8 args go into the frame
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// Create the frame index object for this incoming parameter...
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ArgOffset = 16 + 8 * (count - 8);
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int FI = MFI->CreateFixedObject(8, ArgOffset);
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
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argt = newroot = DAG.getLoad(getValueType(I->getType()), dl,
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DAG.getEntryNode(), FIN, NULL, 0);
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}
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++count;
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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}
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// Create a vreg to hold the output of (what will become)
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// the "alloc" instruction
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VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
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BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
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// we create a PSEUDO_ALLOC (pseudo)instruction for now
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/*
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BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
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// hmm:
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BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
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BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
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// ..hmm.
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BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
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// hmm:
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BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
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BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
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// ..hmm.
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*/
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unsigned tempOffset=0;
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// if this is a varargs function, we simply lower llvm.va_start by
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// pointing to the first entry
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if(F.isVarArg()) {
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tempOffset=0;
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VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
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}
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// here we actually do the moving of args, and store them to the stack
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// too if this is a varargs function:
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for (int i = 0; i < count && i < 8; ++i) {
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BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
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if(F.isVarArg()) {
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// if this is a varargs function, we copy the input registers to the stack
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int FI = MFI->CreateFixedObject(8, tempOffset);
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tempOffset+=8; //XXX: is it safe to use r22 like this?
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BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
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// FIXME: we should use st8.spill here, one day
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BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
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}
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}
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// Finally, inform the code generator which regs we return values in.
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// (see the ISD::RET: case in the instruction selector)
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switch (getValueType(F.getReturnType()).getSimpleVT()) {
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default: assert(0 && "i have no idea where to return this type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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MF.getRegInfo().addLiveOut(IA64::r8);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.getRegInfo().addLiveOut(IA64::F8);
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break;
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}
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}
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std::pair<SDValue, SDValue>
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IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
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bool RetSExt, bool RetZExt, bool isVarArg,
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bool isInreg, unsigned NumFixedArgs,
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unsigned CallingConv,
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bool isTailCall, SDValue Callee,
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ArgListTy &Args, SelectionDAG &DAG,
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DebugLoc dl) {
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MachineFunction &MF = DAG.getMachineFunction();
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unsigned NumBytes = 16;
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unsigned outRegsUsed = 0;
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if (Args.size() > 8) {
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NumBytes += (Args.size() - 8) * 8;
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outRegsUsed = 8;
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} else {
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outRegsUsed = Args.size();
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}
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// FIXME? this WILL fail if we ever try to pass around an arg that
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// consumes more than a single output slot (a 'real' double, int128
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// some sort of aggregate etc.), as we'll underestimate how many 'outX'
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// registers we use. Hopefully, the assembler will notice.
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MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
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std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
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// keep stack frame 16-byte aligned
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// assert(NumBytes==((NumBytes+15) & ~15) &&
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// "stack frame not 16-byte aligned!");
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NumBytes = (NumBytes+15) & ~15;
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
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SDValue StackPtr;
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std::vector<SDValue> Stores;
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std::vector<SDValue> Converts;
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std::vector<SDValue> RegValuesToPass;
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unsigned ArgOffset = 16;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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SDValue Val = Args[i].Node;
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MVT ObjectVT = Val.getValueType();
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SDValue ValToStore(0, 0), ValToConvert(0, 0);
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unsigned ObjSize=8;
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switch (ObjectVT.getSimpleVT()) {
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default: assert(0 && "unexpected argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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//promote to 64-bits, sign/zero extending based on type
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//of the argument
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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if (Args[i].isSExt)
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ExtendKind = ISD::SIGN_EXTEND;
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else if (Args[i].isZExt)
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ExtendKind = ISD::ZERO_EXTEND;
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Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val);
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// XXX: fall through
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}
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case MVT::i64:
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//ObjSize = 8;
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if(RegValuesToPass.size() >= 8) {
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ValToStore = Val;
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} else {
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RegValuesToPass.push_back(Val);
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}
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break;
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case MVT::f32:
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//promote to 64-bits
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Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
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// XXX: fall through
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case MVT::f64:
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if(RegValuesToPass.size() >= 8) {
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ValToStore = Val;
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} else {
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RegValuesToPass.push_back(Val);
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if(1 /* TODO: if(calling external or varadic function)*/ ) {
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ValToConvert = Val; // additionally pass this FP value as an int
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}
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}
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break;
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}
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if(ValToStore.getNode()) {
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if(!StackPtr.getNode()) {
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StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
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}
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SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff);
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Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0));
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ArgOffset += ObjSize;
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}
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if(ValToConvert.getNode()) {
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Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl,
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MVT::i64, ValToConvert));
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}
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}
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// Emit all stores, make sure they occur before any copies into physregs.
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if (!Stores.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl,
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MVT::Other, &Stores[0],Stores.size());
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static const unsigned IntArgRegs[] = {
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IA64::out0, IA64::out1, IA64::out2, IA64::out3,
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IA64::out4, IA64::out5, IA64::out6, IA64::out7
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};
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static const unsigned FPArgRegs[] = {
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IA64::F8, IA64::F9, IA64::F10, IA64::F11,
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IA64::F12, IA64::F13, IA64::F14, IA64::F15
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};
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|
SDValue InFlag;
|
|
|
|
// save the current GP, SP and RP : FIXME: do we need to do all 3 always?
|
|
SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1,
|
|
MVT::i64, InFlag);
|
|
Chain = GPBeforeCall.getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12,
|
|
MVT::i64, InFlag);
|
|
Chain = SPBeforeCall.getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp,
|
|
MVT::i64, InFlag);
|
|
Chain = RPBeforeCall.getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
|
// and flag operands which copy the outgoing integer args into regs out[0-7]
|
|
// mapped 1:1 and the FP args into regs F8-F15 "lazily"
|
|
// TODO: for performance, we should only copy FP args into int regs when we
|
|
// know this is required (i.e. for varardic or external (unknown) functions)
|
|
|
|
// first to the FP->(integer representation) conversions, these are
|
|
// flagged for now, but shouldn't have to be (TODO)
|
|
unsigned seenConverts = 0;
|
|
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
|
if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
|
|
Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i],
|
|
Converts[seenConverts++], InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
}
|
|
|
|
// next copy args into the usual places, these are flagged
|
|
unsigned usedFPArgs = 0;
|
|
for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
|
|
Chain = DAG.getCopyToReg(Chain, dl,
|
|
RegValuesToPass[i].getValueType().isInteger() ?
|
|
IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
|
/*
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
|
|
}
|
|
*/
|
|
|
|
std::vector<MVT> NodeTys;
|
|
std::vector<SDValue> CallOperands;
|
|
NodeTys.push_back(MVT::Other); // Returns a chain
|
|
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
|
|
CallOperands.push_back(Chain);
|
|
CallOperands.push_back(Callee);
|
|
|
|
// emit the call itself
|
|
if (InFlag.getNode())
|
|
CallOperands.push_back(InFlag);
|
|
else
|
|
assert(0 && "this should never happen!\n");
|
|
|
|
// to make way for a hack:
|
|
Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
|
|
&CallOperands[0], CallOperands.size());
|
|
InFlag = Chain.getValue(1);
|
|
|
|
// restore the GP, SP and RP after the call
|
|
Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
std::vector<MVT> RetVals;
|
|
RetVals.push_back(MVT::Other);
|
|
RetVals.push_back(MVT::Flag);
|
|
|
|
MVT RetTyVT = getValueType(RetTy);
|
|
SDValue RetVal;
|
|
if (RetTyVT != MVT::isVoid) {
|
|
switch (RetTyVT.getSimpleVT()) {
|
|
default: assert(0 && "Unknown value type to return!");
|
|
case MVT::i1: { // bools are just like other integers (returned in r8)
|
|
// we *could* fall through to the truncate below, but this saves a
|
|
// few redundant predicate ops
|
|
SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8,
|
|
MVT::i64,InFlag);
|
|
InFlag = boolInR8.getValue(2);
|
|
Chain = boolInR8.getValue(1);
|
|
SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0,
|
|
MVT::i64, InFlag);
|
|
InFlag = zeroReg.getValue(2);
|
|
Chain = zeroReg.getValue(1);
|
|
|
|
RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE);
|
|
break;
|
|
}
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
|
|
// keep track of whether it is sign or zero extended (todo: bools?)
|
|
/* XXX
|
|
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
|
|
dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT));
|
|
*/
|
|
RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
|
|
break;
|
|
case MVT::i64:
|
|
RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
InFlag = RetVal.getValue(2); // XXX dead
|
|
break;
|
|
case MVT::f32:
|
|
RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
|
|
DAG.getIntPtrConstant(0));
|
|
break;
|
|
case MVT::f64:
|
|
RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
|
|
Chain = RetVal.getValue(1);
|
|
InFlag = RetVal.getValue(2); // XXX dead
|
|
break;
|
|
}
|
|
}
|
|
|
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
|
DAG.getIntPtrConstant(0, true), SDValue());
|
|
return std::make_pair(RetVal, Chain);
|
|
}
|
|
|
|
SDValue IA64TargetLowering::
|
|
LowerOperation(SDValue Op, SelectionDAG &DAG) {
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
switch (Op.getOpcode()) {
|
|
default: assert(0 && "Should not custom lower this!");
|
|
case ISD::GlobalTLSAddress:
|
|
assert(0 && "TLS not implemented for IA64.");
|
|
case ISD::RET: {
|
|
SDValue AR_PFSVal, Copy;
|
|
|
|
switch(Op.getNumOperands()) {
|
|
default:
|
|
assert(0 && "Do not know how to return this many arguments!");
|
|
abort();
|
|
case 1:
|
|
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
|
|
AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,
|
|
AR_PFSVal);
|
|
return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal);
|
|
case 3: {
|
|
// Copy the result into the output register & restore ar.pfs
|
|
MVT ArgVT = Op.getOperand(1).getValueType();
|
|
unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
|
|
|
|
AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
|
|
Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg,
|
|
Op.getOperand(1), SDValue());
|
|
AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl,
|
|
IA64::AR_PFS, AR_PFSVal, Copy.getValue(1));
|
|
return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other,
|
|
AR_PFSVal, AR_PFSVal.getValue(1));
|
|
}
|
|
}
|
|
return SDValue();
|
|
}
|
|
case ISD::VAARG: {
|
|
MVT VT = getPointerTy();
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1),
|
|
SV, 0);
|
|
// Increment the pointer, VAList, to the next vaarg
|
|
SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList,
|
|
DAG.getConstant(VT.getSizeInBits()/8,
|
|
VT));
|
|
// Store the incremented VAList to the legalized pointer
|
|
VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr,
|
|
Op.getOperand(1), SV, 0);
|
|
// Load the actual argument out of the pointer VAList
|
|
return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0);
|
|
}
|
|
case ISD::VASTART: {
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
// memory location argument.
|
|
SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
|
return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
|
|
}
|
|
// Frame & Return address. Currently unimplemented
|
|
case ISD::RETURNADDR: break;
|
|
case ISD::FRAMEADDR: break;
|
|
}
|
|
return SDValue();
|
|
}
|