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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
958 lines
34 KiB
C++
958 lines
34 KiB
C++
//=======- PPCFrameInfo.cpp - PPC Frame Information ------------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PPC implementation of TargetFrameInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCFrameInfo.h"
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#include "PPCInstrInfo.h"
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#include "PPCMachineFunctionInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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// FIXME This disables some code that aligns the stack to a boundary bigger than
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// the default (16 bytes on Darwin) when there is a stack local of greater
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// alignment. This does not currently work, because the delta between old and
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// new stack pointers is added to offsets that reference incoming parameters
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// after the prolog is generated, and the code that does that doesn't handle a
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// variable delta. You don't want to do that anyway; a better approach is to
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// reserve another register that retains to the incoming stack pointer, and
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// reference parameters relative to that.
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#define ALIGN_STACK 0
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/// VRRegNo - Map from a numbered VR register to its enum value.
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///
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static const unsigned short VRRegNo[] = {
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PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
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PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
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};
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/// RemoveVRSaveCode - We have found that this function does not need any code
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/// to manipulate the VRSAVE register, even though it uses vector registers.
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/// This can happen when the only registers used are known to be live in or out
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/// of the function. Remove all of the VRSAVE related code from the function.
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static void RemoveVRSaveCode(MachineInstr *MI) {
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MachineBasicBlock *Entry = MI->getParent();
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MachineFunction *MF = Entry->getParent();
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// We know that the MTVRSAVE instruction immediately follows MI. Remove it.
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MachineBasicBlock::iterator MBBI = MI;
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++MBBI;
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assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
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MBBI->eraseFromParent();
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bool RemovedAllMTVRSAVEs = true;
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// See if we can find and remove the MTVRSAVE instruction from all of the
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// epilog blocks.
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for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
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// If last instruction is a return instruction, add an epilogue
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if (!I->empty() && I->back().getDesc().isReturn()) {
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bool FoundIt = false;
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for (MBBI = I->end(); MBBI != I->begin(); ) {
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--MBBI;
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if (MBBI->getOpcode() == PPC::MTVRSAVE) {
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MBBI->eraseFromParent(); // remove it.
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FoundIt = true;
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break;
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}
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}
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RemovedAllMTVRSAVEs &= FoundIt;
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}
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}
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// If we found and removed all MTVRSAVE instructions, remove the read of
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// VRSAVE as well.
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if (RemovedAllMTVRSAVEs) {
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MBBI = MI;
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assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
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--MBBI;
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assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
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MBBI->eraseFromParent();
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}
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// Finally, nuke the UPDATE_VRSAVE.
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MI->eraseFromParent();
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}
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// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
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// instruction selector. Based on the vector registers that have been used,
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// transform this into the appropriate ORI instruction.
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static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
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MachineFunction *MF = MI->getParent()->getParent();
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DebugLoc dl = MI->getDebugLoc();
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unsigned UsedRegMask = 0;
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for (unsigned i = 0; i != 32; ++i)
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if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
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UsedRegMask |= 1 << (31-i);
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// Live in and live out values already must be in the mask, so don't bother
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// marking them.
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for (MachineRegisterInfo::livein_iterator
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I = MF->getRegInfo().livein_begin(),
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E = MF->getRegInfo().livein_end(); I != E; ++I) {
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unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
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if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
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UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
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}
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for (MachineRegisterInfo::liveout_iterator
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I = MF->getRegInfo().liveout_begin(),
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E = MF->getRegInfo().liveout_end(); I != E; ++I) {
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unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
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if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
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UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
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}
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// If no registers are used, turn this into a copy.
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if (UsedRegMask == 0) {
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// Remove all VRSAVE code.
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RemoveVRSaveCode(MI);
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return;
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}
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DstReg = MI->getOperand(0).getReg();
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if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
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if (DstReg != SrcReg)
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
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.addReg(SrcReg)
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.addImm(UsedRegMask);
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else
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
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.addReg(SrcReg, RegState::Kill)
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.addImm(UsedRegMask);
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} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
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if (DstReg != SrcReg)
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
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.addReg(SrcReg)
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.addImm(UsedRegMask >> 16);
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else
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
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.addReg(SrcReg, RegState::Kill)
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.addImm(UsedRegMask >> 16);
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} else {
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if (DstReg != SrcReg)
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
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.addReg(SrcReg)
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.addImm(UsedRegMask >> 16);
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else
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
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.addReg(SrcReg, RegState::Kill)
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.addImm(UsedRegMask >> 16);
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BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
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.addReg(DstReg, RegState::Kill)
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.addImm(UsedRegMask & 0xFFFF);
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}
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// Remove the old UPDATE_VRSAVE instruction.
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MI->eraseFromParent();
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}
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/// determineFrameLayout - Determine the size of the frame and maximum call
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/// frame size.
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void PPCFrameInfo::determineFrameLayout(MachineFunction &MF) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes to allocate from the FrameInfo
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unsigned FrameSize = MFI->getStackSize();
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// Get the alignments provided by the target, and the maximum alignment
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// (if any) of the fixed frame objects.
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unsigned MaxAlign = MFI->getMaxAlignment();
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unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned AlignMask = TargetAlign - 1; //
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// If we are a leaf function, and use up to 224 bytes of stack space,
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// don't have a frame pointer, calls, or dynamic alloca then we do not need
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// to adjust the stack pointer (we fit in the Red Zone).
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bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
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// FIXME SVR4 The 32-bit SVR4 ABI has no red zone.
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if (!DisableRedZone &&
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FrameSize <= 224 && // Fits in red zone.
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!MFI->hasVarSizedObjects() && // No dynamic alloca.
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!MFI->adjustsStack() && // No calls.
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(!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
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// No need for frame
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MFI->setStackSize(0);
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return;
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}
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// Get the maximum call frame size of all the calls.
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unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
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// Maximum call frame needs to be at least big enough for linkage and 8 args.
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unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
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Subtarget.isDarwinABI());
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maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
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// If we have dynamic alloca then maxCallFrameSize needs to be aligned so
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// that allocations will be aligned.
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if (MFI->hasVarSizedObjects())
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maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
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// Update maximum call frame size.
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MFI->setMaxCallFrameSize(maxCallFrameSize);
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// Include call frame size in total.
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FrameSize += maxCallFrameSize;
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// Make sure the frame is aligned.
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FrameSize = (FrameSize + AlignMask) & ~AlignMask;
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// Update frame info.
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MFI->setStackSize(FrameSize);
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}
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// hasFP - Return true if the specified function actually has a dedicated frame
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// pointer register.
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bool PPCFrameInfo::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Naked functions have no stack frame pushed, so we don't have a frame
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// pointer.
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if (MF.getFunction()->hasFnAttr(Attribute::Naked))
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return false;
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return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() ||
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(GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
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}
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void PPCFrameInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const PPCInstrInfo &TII =
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*static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineModuleInfo &MMI = MF.getMMI();
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DebugLoc dl;
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bool needsFrameMoves = MMI.hasDebugInfo() ||
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!MF.getFunction()->doesNotThrow() ||
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UnwindTablesMandatory;
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// Prepare for frame info.
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MCSymbol *FrameLabel = 0;
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// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
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// process it.
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for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
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if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
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HandleVRSaveUpdate(MBBI, TII);
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break;
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}
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}
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// Move MBBI back to the beginning of the function.
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MBBI = MBB.begin();
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// Work out frame sizes.
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determineFrameLayout(MF);
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unsigned FrameSize = MFI->getStackSize();
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int NegFrameSize = -FrameSize;
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// Get processor type.
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bool isPPC64 = Subtarget.isPPC64();
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// Get operating system
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bool isDarwinABI = Subtarget.isDarwinABI();
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// Check if the link register (LR) must be saved.
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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bool MustSaveLR = FI->mustSaveLR();
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// Do we have a frame pointer for this function?
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bool HasFP = hasFP(MF) && FrameSize;
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int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
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int FPOffset = 0;
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if (HasFP) {
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if (Subtarget.isSVR4ABI()) {
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MachineFrameInfo *FFI = MF.getFrameInfo();
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int FPIndex = FI->getFramePointerSaveIndex();
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assert(FPIndex && "No Frame Pointer Save Slot!");
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FPOffset = FFI->getObjectOffset(FPIndex);
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} else {
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FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
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}
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}
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if (isPPC64) {
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
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if (HasFP)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
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.addReg(PPC::X31)
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.addImm(FPOffset/4)
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.addReg(PPC::X1);
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
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.addReg(PPC::X0)
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.addImm(LROffset / 4)
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.addReg(PPC::X1);
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} else {
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
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if (HasFP)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
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.addReg(PPC::R31)
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.addImm(FPOffset)
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.addReg(PPC::R1);
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
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.addReg(PPC::R0)
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.addImm(LROffset)
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.addReg(PPC::R1);
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}
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// Skip if a leaf routine.
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if (!FrameSize) return;
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// Get stack alignments.
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unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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// Adjust stack pointer: r1 += NegFrameSize.
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// If there is a preferred stack alignment, align R1 now
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if (!isPPC64) {
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// PPC32.
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if (ALIGN_STACK && MaxAlign > TargetAlign) {
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assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
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"Invalid alignment!");
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assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
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.addReg(PPC::R1)
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.addImm(0)
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.addImm(32 - Log2_32(MaxAlign))
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.addImm(31);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(NegFrameSize);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
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.addReg(PPC::R1)
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.addReg(PPC::R1)
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.addReg(PPC::R0);
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} else if (isInt<16>(NegFrameSize)) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
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.addReg(PPC::R1)
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.addImm(NegFrameSize)
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.addReg(PPC::R1);
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} else {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
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.addImm(NegFrameSize >> 16);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(NegFrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
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.addReg(PPC::R1)
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.addReg(PPC::R1)
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.addReg(PPC::R0);
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}
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} else { // PPC64.
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if (ALIGN_STACK && MaxAlign > TargetAlign) {
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assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
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"Invalid alignment!");
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assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
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.addReg(PPC::X1)
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.addImm(0)
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.addImm(64 - Log2_32(MaxAlign));
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
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.addReg(PPC::X0)
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.addImm(NegFrameSize);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
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.addReg(PPC::X1)
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.addReg(PPC::X1)
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.addReg(PPC::X0);
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} else if (isInt<16>(NegFrameSize)) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
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.addReg(PPC::X1)
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.addImm(NegFrameSize / 4)
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.addReg(PPC::X1);
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} else {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
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.addImm(NegFrameSize >> 16);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
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.addReg(PPC::X0, RegState::Kill)
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.addImm(NegFrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
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.addReg(PPC::X1)
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.addReg(PPC::X1)
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.addReg(PPC::X0);
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}
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}
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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// Add the "machine moves" for the instructions we generated above, but in
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// reverse order.
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if (needsFrameMoves) {
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// Mark effective beginning of when frame pointer becomes valid.
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FrameLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
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// Show update of SP.
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if (NegFrameSize) {
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MachineLocation SPDst(MachineLocation::VirtualFP);
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MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
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Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
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} else {
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MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
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Moves.push_back(MachineMove(FrameLabel, SP, SP));
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}
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if (HasFP) {
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MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
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MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
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Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
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}
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if (MustSaveLR) {
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MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
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|
MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
|
|
Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
|
|
}
|
|
}
|
|
|
|
MCSymbol *ReadyLabel = 0;
|
|
|
|
// If there is a frame pointer, copy R1 into R31
|
|
if (HasFP) {
|
|
if (!isPPC64) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
|
|
.addReg(PPC::R1)
|
|
.addReg(PPC::R1);
|
|
} else {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
|
|
.addReg(PPC::X1)
|
|
.addReg(PPC::X1);
|
|
}
|
|
|
|
if (needsFrameMoves) {
|
|
ReadyLabel = MMI.getContext().CreateTempSymbol();
|
|
|
|
// Mark effective beginning of when frame pointer is ready.
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
|
|
|
|
MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
|
|
(isPPC64 ? PPC::X1 : PPC::R1));
|
|
MachineLocation FPSrc(MachineLocation::VirtualFP);
|
|
Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
|
|
}
|
|
}
|
|
|
|
if (needsFrameMoves) {
|
|
MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
|
|
|
|
// Add callee saved registers to move list.
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
|
|
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
|
|
unsigned Reg = CSI[I].getReg();
|
|
if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
|
|
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
|
|
MachineLocation CSSrc(Reg);
|
|
Moves.push_back(MachineMove(Label, CSDst, CSSrc));
|
|
}
|
|
}
|
|
}
|
|
|
|
void PPCFrameInfo::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
const PPCInstrInfo &TII =
|
|
*static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
|
|
|
|
unsigned RetOpcode = MBBI->getOpcode();
|
|
DebugLoc dl;
|
|
|
|
assert((RetOpcode == PPC::BLR ||
|
|
RetOpcode == PPC::TCRETURNri ||
|
|
RetOpcode == PPC::TCRETURNdi ||
|
|
RetOpcode == PPC::TCRETURNai ||
|
|
RetOpcode == PPC::TCRETURNri8 ||
|
|
RetOpcode == PPC::TCRETURNdi8 ||
|
|
RetOpcode == PPC::TCRETURNai8) &&
|
|
"Can only insert epilog into returning blocks");
|
|
|
|
// Get alignment info so we know how to restore r1
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
|
|
|
// Get the number of bytes allocated from the FrameInfo.
|
|
int FrameSize = MFI->getStackSize();
|
|
|
|
// Get processor type.
|
|
bool isPPC64 = Subtarget.isPPC64();
|
|
// Get operating system
|
|
bool isDarwinABI = Subtarget.isDarwinABI();
|
|
// Check if the link register (LR) has been saved.
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
bool MustSaveLR = FI->mustSaveLR();
|
|
// Do we have a frame pointer for this function?
|
|
bool HasFP = hasFP(MF) && FrameSize;
|
|
|
|
int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
|
|
|
|
int FPOffset = 0;
|
|
if (HasFP) {
|
|
if (Subtarget.isSVR4ABI()) {
|
|
MachineFrameInfo *FFI = MF.getFrameInfo();
|
|
int FPIndex = FI->getFramePointerSaveIndex();
|
|
assert(FPIndex && "No Frame Pointer Save Slot!");
|
|
FPOffset = FFI->getObjectOffset(FPIndex);
|
|
} else {
|
|
FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
|
|
}
|
|
}
|
|
|
|
bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
|
|
RetOpcode == PPC::TCRETURNdi ||
|
|
RetOpcode == PPC::TCRETURNai ||
|
|
RetOpcode == PPC::TCRETURNri8 ||
|
|
RetOpcode == PPC::TCRETURNdi8 ||
|
|
RetOpcode == PPC::TCRETURNai8;
|
|
|
|
if (UsesTCRet) {
|
|
int MaxTCRetDelta = FI->getTailCallSPDelta();
|
|
MachineOperand &StackAdjust = MBBI->getOperand(1);
|
|
assert(StackAdjust.isImm() && "Expecting immediate value.");
|
|
// Adjust stack pointer.
|
|
int StackAdj = StackAdjust.getImm();
|
|
int Delta = StackAdj - MaxTCRetDelta;
|
|
assert((Delta >= 0) && "Delta must be positive");
|
|
if (MaxTCRetDelta>0)
|
|
FrameSize += (StackAdj +Delta);
|
|
else
|
|
FrameSize += StackAdj;
|
|
}
|
|
|
|
if (FrameSize) {
|
|
// The loaded (or persistent) stack pointer value is offset by the 'stwu'
|
|
// on entry to the function. Add this offset back now.
|
|
if (!isPPC64) {
|
|
// If this function contained a fastcc call and GuaranteedTailCallOpt is
|
|
// enabled (=> hasFastCall()==true) the fastcc call might contain a tail
|
|
// call which invalidates the stack pointer value in SP(0). So we use the
|
|
// value of R31 in this case.
|
|
if (FI->hasFastCall() && isInt<16>(FrameSize)) {
|
|
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
|
|
.addReg(PPC::R31).addImm(FrameSize);
|
|
} else if(FI->hasFastCall()) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
|
|
.addImm(FrameSize >> 16);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
|
|
.addReg(PPC::R0, RegState::Kill)
|
|
.addImm(FrameSize & 0xFFFF);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
|
|
.addReg(PPC::R1)
|
|
.addReg(PPC::R31)
|
|
.addReg(PPC::R0);
|
|
} else if (isInt<16>(FrameSize) &&
|
|
(!ALIGN_STACK || TargetAlign >= MaxAlign) &&
|
|
!MFI->hasVarSizedObjects()) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
|
|
.addReg(PPC::R1).addImm(FrameSize);
|
|
} else {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
|
|
.addImm(0).addReg(PPC::R1);
|
|
}
|
|
} else {
|
|
if (FI->hasFastCall() && isInt<16>(FrameSize)) {
|
|
assert(hasFP(MF) && "Expecting a valid the frame pointer.");
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
|
|
.addReg(PPC::X31).addImm(FrameSize);
|
|
} else if(FI->hasFastCall()) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
|
|
.addImm(FrameSize >> 16);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
|
|
.addReg(PPC::X0, RegState::Kill)
|
|
.addImm(FrameSize & 0xFFFF);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
|
|
.addReg(PPC::X1)
|
|
.addReg(PPC::X31)
|
|
.addReg(PPC::X0);
|
|
} else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
|
|
!MFI->hasVarSizedObjects()) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
|
|
.addReg(PPC::X1).addImm(FrameSize);
|
|
} else {
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
|
|
.addImm(0).addReg(PPC::X1);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (isPPC64) {
|
|
if (MustSaveLR)
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
|
|
.addImm(LROffset/4).addReg(PPC::X1);
|
|
|
|
if (HasFP)
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
|
|
.addImm(FPOffset/4).addReg(PPC::X1);
|
|
|
|
if (MustSaveLR)
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
|
|
} else {
|
|
if (MustSaveLR)
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
|
|
.addImm(LROffset).addReg(PPC::R1);
|
|
|
|
if (HasFP)
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
|
|
.addImm(FPOffset).addReg(PPC::R1);
|
|
|
|
if (MustSaveLR)
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
|
|
}
|
|
|
|
// Callee pop calling convention. Pop parameter/linkage area. Used for tail
|
|
// call optimization
|
|
if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
|
|
MF.getFunction()->getCallingConv() == CallingConv::Fast) {
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
unsigned CallerAllocatedAmt = FI->getMinReservedArea();
|
|
unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
|
|
unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
|
|
unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
|
|
unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
|
|
unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
|
|
unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
|
|
unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
|
|
|
|
if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
|
|
BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
|
|
.addReg(StackReg).addImm(CallerAllocatedAmt);
|
|
} else {
|
|
BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
|
|
.addImm(CallerAllocatedAmt >> 16);
|
|
BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
|
|
.addReg(TmpReg, RegState::Kill)
|
|
.addImm(CallerAllocatedAmt & 0xFFFF);
|
|
BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
|
|
.addReg(StackReg)
|
|
.addReg(FPReg)
|
|
.addReg(TmpReg);
|
|
}
|
|
} else if (RetOpcode == PPC::TCRETURNdi) {
|
|
MBBI = prior(MBB.end());
|
|
MachineOperand &JumpTarget = MBBI->getOperand(0);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
|
|
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
|
|
} else if (RetOpcode == PPC::TCRETURNri) {
|
|
MBBI = prior(MBB.end());
|
|
assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
|
|
} else if (RetOpcode == PPC::TCRETURNai) {
|
|
MBBI = prior(MBB.end());
|
|
MachineOperand &JumpTarget = MBBI->getOperand(0);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
|
|
} else if (RetOpcode == PPC::TCRETURNdi8) {
|
|
MBBI = prior(MBB.end());
|
|
MachineOperand &JumpTarget = MBBI->getOperand(0);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
|
|
addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
|
|
} else if (RetOpcode == PPC::TCRETURNri8) {
|
|
MBBI = prior(MBB.end());
|
|
assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
|
|
} else if (RetOpcode == PPC::TCRETURNai8) {
|
|
MBBI = prior(MBB.end());
|
|
MachineOperand &JumpTarget = MBBI->getOperand(0);
|
|
BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
|
|
}
|
|
}
|
|
|
|
void PPCFrameInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
|
|
// Initial state of the frame pointer is R1.
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
MachineLocation Src(PPC::R1, 0);
|
|
Moves.push_back(MachineMove(0, Dst, Src));
|
|
}
|
|
|
|
static bool spillsCR(const MachineFunction &MF) {
|
|
const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
return FuncInfo->isCRSpilled();
|
|
}
|
|
|
|
/// MustSaveLR - Return true if this function requires that we save the LR
|
|
/// register onto the stack in the prolog and restore it in the epilog of the
|
|
/// function.
|
|
static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
|
|
const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
// We need a save/restore of LR if there is any def of LR (which is
|
|
// defined by calls, including the PIC setup sequence), or if there is
|
|
// some use of the LR stack slot (e.g. for builtin_return_address).
|
|
// (LR comes in 32 and 64 bit versions.)
|
|
MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
|
|
return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
|
|
}
|
|
|
|
void
|
|
PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS) const {
|
|
const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
|
|
|
|
// Save and clear the LR state.
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
unsigned LR = RegInfo->getRARegister();
|
|
FI->setMustSaveLR(MustSaveLR(MF, LR));
|
|
MF.getRegInfo().setPhysRegUnused(LR);
|
|
|
|
// Save R31 if necessary
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
|
bool isPPC64 = Subtarget.isPPC64();
|
|
bool isDarwinABI = Subtarget.isDarwinABI();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// If the frame pointer save index hasn't been defined yet.
|
|
if (!FPSI && hasFP(MF)) {
|
|
// Find out what the fix offset of the frame pointer save area.
|
|
int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
|
|
// Allocate the frame index for frame pointer save area.
|
|
FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
|
|
// Save the result.
|
|
FI->setFramePointerSaveIndex(FPSI);
|
|
}
|
|
|
|
// Reserve stack space to move the linkage area to in case of a tail call.
|
|
int TCSPDelta = 0;
|
|
if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
|
|
MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
|
|
}
|
|
|
|
// Reserve a slot closest to SP or frame pointer if we have a dynalloc or
|
|
// a large stack, which will require scavenging a register to materialize a
|
|
// large offset.
|
|
// FIXME: this doesn't actually check stack size, so is a bit pessimistic
|
|
// FIXME: doesn't detect whether or not we need to spill vXX, which requires
|
|
// r0 for now.
|
|
|
|
if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable.
|
|
if (hasFP(MF) || spillsCR(MF)) {
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
|
|
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
|
|
RC->getAlignment(),
|
|
false));
|
|
}
|
|
}
|
|
|
|
void PPCFrameInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
|
|
const {
|
|
// Early exit if not using the SVR4 ABI.
|
|
if (!Subtarget.isSVR4ABI())
|
|
return;
|
|
|
|
// Get callee saved register information.
|
|
MachineFrameInfo *FFI = MF.getFrameInfo();
|
|
const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
|
|
|
|
// Early exit if no callee saved registers are modified!
|
|
if (CSI.empty() && !hasFP(MF)) {
|
|
return;
|
|
}
|
|
|
|
unsigned MinGPR = PPC::R31;
|
|
unsigned MinG8R = PPC::X31;
|
|
unsigned MinFPR = PPC::F31;
|
|
unsigned MinVR = PPC::V31;
|
|
|
|
bool HasGPSaveArea = false;
|
|
bool HasG8SaveArea = false;
|
|
bool HasFPSaveArea = false;
|
|
bool HasCRSaveArea = false;
|
|
bool HasVRSAVESaveArea = false;
|
|
bool HasVRSaveArea = false;
|
|
|
|
SmallVector<CalleeSavedInfo, 18> GPRegs;
|
|
SmallVector<CalleeSavedInfo, 18> G8Regs;
|
|
SmallVector<CalleeSavedInfo, 18> FPRegs;
|
|
SmallVector<CalleeSavedInfo, 18> VRegs;
|
|
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
unsigned Reg = CSI[i].getReg();
|
|
if (PPC::GPRCRegisterClass->contains(Reg)) {
|
|
HasGPSaveArea = true;
|
|
|
|
GPRegs.push_back(CSI[i]);
|
|
|
|
if (Reg < MinGPR) {
|
|
MinGPR = Reg;
|
|
}
|
|
} else if (PPC::G8RCRegisterClass->contains(Reg)) {
|
|
HasG8SaveArea = true;
|
|
|
|
G8Regs.push_back(CSI[i]);
|
|
|
|
if (Reg < MinG8R) {
|
|
MinG8R = Reg;
|
|
}
|
|
} else if (PPC::F8RCRegisterClass->contains(Reg)) {
|
|
HasFPSaveArea = true;
|
|
|
|
FPRegs.push_back(CSI[i]);
|
|
|
|
if (Reg < MinFPR) {
|
|
MinFPR = Reg;
|
|
}
|
|
// FIXME SVR4: Disable CR save area for now.
|
|
} else if (PPC::CRBITRCRegisterClass->contains(Reg)
|
|
|| PPC::CRRCRegisterClass->contains(Reg)) {
|
|
// HasCRSaveArea = true;
|
|
} else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
|
|
HasVRSAVESaveArea = true;
|
|
} else if (PPC::VRRCRegisterClass->contains(Reg)) {
|
|
HasVRSaveArea = true;
|
|
|
|
VRegs.push_back(CSI[i]);
|
|
|
|
if (Reg < MinVR) {
|
|
MinVR = Reg;
|
|
}
|
|
} else {
|
|
llvm_unreachable("Unknown RegisterClass!");
|
|
}
|
|
}
|
|
|
|
PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
int64_t LowerBound = 0;
|
|
|
|
// Take into account stack space reserved for tail calls.
|
|
int TCSPDelta = 0;
|
|
if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
|
|
LowerBound = TCSPDelta;
|
|
}
|
|
|
|
// The Floating-point register save area is right below the back chain word
|
|
// of the previous stack frame.
|
|
if (HasFPSaveArea) {
|
|
for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
|
|
int FI = FPRegs[i].getFrameIdx();
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
|
|
LowerBound -= (31 - PPCRegisterInfo::getRegisterNumbering(MinFPR) + 1) * 8;
|
|
}
|
|
|
|
// Check whether the frame pointer register is allocated. If so, make sure it
|
|
// is spilled to the correct offset.
|
|
if (hasFP(MF)) {
|
|
HasGPSaveArea = true;
|
|
|
|
int FI = PFI->getFramePointerSaveIndex();
|
|
assert(FI && "No Frame Pointer Save Slot!");
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
|
|
// General register save area starts right below the Floating-point
|
|
// register save area.
|
|
if (HasGPSaveArea || HasG8SaveArea) {
|
|
// Move general register save area spill slots down, taking into account
|
|
// the size of the Floating-point register save area.
|
|
for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
|
|
int FI = GPRegs[i].getFrameIdx();
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
|
|
// Move general register save area spill slots down, taking into account
|
|
// the size of the Floating-point register save area.
|
|
for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
|
|
int FI = G8Regs[i].getFrameIdx();
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
|
|
unsigned MinReg =
|
|
std::min<unsigned>(PPCRegisterInfo::getRegisterNumbering(MinGPR),
|
|
PPCRegisterInfo::getRegisterNumbering(MinG8R));
|
|
|
|
if (Subtarget.isPPC64()) {
|
|
LowerBound -= (31 - MinReg + 1) * 8;
|
|
} else {
|
|
LowerBound -= (31 - MinReg + 1) * 4;
|
|
}
|
|
}
|
|
|
|
// The CR save area is below the general register save area.
|
|
if (HasCRSaveArea) {
|
|
// FIXME SVR4: Is it actually possible to have multiple elements in CSI
|
|
// which have the CR/CRBIT register class?
|
|
// Adjust the frame index of the CR spill slot.
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
unsigned Reg = CSI[i].getReg();
|
|
|
|
if (PPC::CRBITRCRegisterClass->contains(Reg) ||
|
|
PPC::CRRCRegisterClass->contains(Reg)) {
|
|
int FI = CSI[i].getFrameIdx();
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
}
|
|
|
|
LowerBound -= 4; // The CR save area is always 4 bytes long.
|
|
}
|
|
|
|
if (HasVRSAVESaveArea) {
|
|
// FIXME SVR4: Is it actually possible to have multiple elements in CSI
|
|
// which have the VRSAVE register class?
|
|
// Adjust the frame index of the VRSAVE spill slot.
|
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
unsigned Reg = CSI[i].getReg();
|
|
|
|
if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
|
|
int FI = CSI[i].getFrameIdx();
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
}
|
|
|
|
LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
|
|
}
|
|
|
|
if (HasVRSaveArea) {
|
|
// Insert alignment padding, we need 16-byte alignment.
|
|
LowerBound = (LowerBound - 15) & ~(15);
|
|
|
|
for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
|
|
int FI = VRegs[i].getFrameIdx();
|
|
|
|
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
|
|
}
|
|
}
|
|
}
|