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The frame object which points to the dynamically allocated area will not be needed after changes are made to cease reserving call frames. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161076 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
7.9 KiB
C++
225 lines
7.9 KiB
C++
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsISELLOWERING_H
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#define MipsISELLOWERING_H
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Jump and link (call)
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JmpLink,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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Hi,
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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Lo,
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Thread Pointer
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ThreadPointer,
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// Floating Point Branch Conditional
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FPBrcond,
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// Floating Point Compare
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FPCmp,
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// Floating Point Conditional Moves
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CMovFP_T,
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CMovFP_F,
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// Floating Point Rounding
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FPRound,
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// Return
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Ret,
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// MAdd/Sub nodes
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MAdd,
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MAddu,
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MSub,
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MSubu,
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// DivRem(u)
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DivRem,
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DivRemU,
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BuildPairF64,
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ExtractElementF64,
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Wrapper,
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DynAlloc,
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Sync,
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Ext,
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Ins,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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SWL,
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SWR,
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LDL,
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LDR,
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SDL,
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SDR
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsTargetLowering : public TargetLowering {
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public:
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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EVT getSetCCResultType(EVT VT) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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private:
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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bool HasMips64, IsN64, IsO32;
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// Lower Operand helpers
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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// Lower Operand specifics
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
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bool IsSRA) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsZeroVal,
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bool MemcpyStrSrc,
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MachineFunction &MF) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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virtual unsigned getJumpTableEncoding() const;
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MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size, unsigned BinOpcode, bool Nand = false) const;
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MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
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bool Nand = false) const;
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MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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};
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}
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#endif // MipsISELLOWERING_H
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