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When unsafe FP math operations are enabled, we can use the fre[s] and frsqrte[s] instructions, which generate reciprocal (sqrt) estimates, together with some Newton iteration, in order to quickly generate floating-point division and sqrt results. All of these instructions are separately optional, and so each has its own feature flag (except for the Altivec instructions, which are covered under the existing Altivec flag). Doing this is not only faster than using the IEEE-compliant fdiv/fsqrt instructions, but allows these computations to be pipelined with other computations in order to hide their overall latency. I've also added a couple of missing fnmsub patterns which turned out to be missing (but are necessary for good code generation of the Newton iterations). Altivec needs a similar fix, but that will probably be more complicated because fneg is expanded for Altivec's v4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178617 91177308-0d34-0410-b5e6-96231b3b80d8
160 lines
5.2 KiB
C++
160 lines
5.2 KiB
C++
//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the PPC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCSubtarget.h"
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#include "PPC.h"
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#include "PPCRegisterInfo.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cstdlib>
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "PPCGenSubtargetInfo.inc"
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using namespace llvm;
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PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool is64Bit)
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: PPCGenSubtargetInfo(TT, CPU, FS)
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, StackAlignment(16)
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, DarwinDirective(PPC::DIR_NONE)
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, HasMFOCRF(false)
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, Has64BitSupport(false)
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, Use64BitRegs(false)
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, IsPPC64(is64Bit)
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, HasAltivec(false)
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, HasQPX(false)
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, HasFSQRT(false)
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, HasFRE(false)
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, HasFRES(false)
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, HasFRSQRTE(false)
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, HasFRSQRTES(false)
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, HasRecipPrec(false)
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, HasSTFIWX(false)
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, HasLFIWAX(false)
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, HasFPRND(false)
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, HasFPCVT(false)
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, HasISEL(false)
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, HasPOPCNTD(false)
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, HasLDBRX(false)
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, IsBookE(false)
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, HasLazyResolverStubs(false)
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, IsJITCodeModel(false)
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, TargetTriple(TT) {
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// Determine default and user specified characteristics
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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#if (defined(__APPLE__) || defined(__linux__)) && \
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(defined(__ppc__) || defined(__powerpc__))
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if (CPUName == "generic")
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CPUName = sys::getHostCPUName();
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#endif
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Make sure 64-bit features are available when CPUname is generic
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std::string FullFS = FS;
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// If we are generating code for ppc64, verify that options make sense.
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if (is64Bit) {
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Has64BitSupport = true;
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// Silently force 64-bit register use on ppc64.
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Use64BitRegs = true;
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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}
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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// If the user requested use of 64-bit regs, but the cpu selected doesn't
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// support it, ignore.
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if (use64BitRegs() && !has64BitSupport())
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Use64BitRegs = false;
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// Set up darwin-specific properties.
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if (isDarwin())
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HasLazyResolverStubs = true;
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// QPX requires a 32-byte aligned stack. Note that we need to do this if
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// we're compiling for a BG/Q system regardless of whether or not QPX
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// is enabled because external functions will assume this alignment.
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if (hasQPX() || isBGQ())
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StackAlignment = 32;
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}
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/// SetJITMode - This is called to inform the subtarget info that we are
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/// producing code for the JIT.
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void PPCSubtarget::SetJITMode() {
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// JIT mode doesn't want lazy resolver stubs, it knows exactly where
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// everything is. This matters for PPC64, which codegens in PIC mode without
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// stubs.
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HasLazyResolverStubs = false;
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// Calls to external functions need to use indirect calls
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IsJITCodeModel = true;
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}
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/// hasLazyResolverStub - Return true if accesses to the specified global have
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/// to go through a dyld lazy resolution stub. This means that an extra load
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/// is required to get the address of the global.
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bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// We never have stubs if HasLazyResolverStubs=false or if in static mode.
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if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
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return false;
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// If symbol visibility is hidden, the extra load is not needed if
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// the symbol is definitely defined in the current translation unit.
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bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
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if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
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return false;
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return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
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GV->hasCommonLinkage() || isDecl;
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}
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bool PPCSubtarget::enablePostRAScheduler(
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CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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// FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
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// but we can't because we can't reassign the cr registers. There is a
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// dependence between the cr register and the RLWINM instruction used
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// to extract its value which the anti-dependency breaker can't currently
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// see. Maybe we should make a late-expanded pseudo to encode this dependency.
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// (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
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Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
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CriticalPathRCs.clear();
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if (isPPC64())
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CriticalPathRCs.push_back(&PPC::G8RCRegClass);
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else
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CriticalPathRCs.push_back(&PPC::GPRCRegClass);
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CriticalPathRCs.push_back(&PPC::F8RCRegClass);
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CriticalPathRCs.push_back(&PPC::VRRCRegClass);
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return OptLevel >= CodeGenOpt::Default;
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}
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