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https://github.com/c64scene-ar/llvm-6502.git
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2584ba5867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5214 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
4.0 KiB
C++
105 lines
4.0 KiB
C++
//===-- llvm/Target/TargetMachine.h - General Target Information -*- C++ -*-==//
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//
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// This file describes the general parts of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETMACHINE_H
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#define LLVM_TARGET_TARGETMACHINE_H
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#include "llvm/Target/TargetData.h"
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#include "Support/NonCopyable.h"
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class TargetInstrInfo;
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class TargetInstrDescriptor;
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class TargetSchedInfo;
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class TargetRegInfo;
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class TargetFrameInfo;
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class TargetCacheInfo;
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class TargetOptInfo;
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class MachineCodeEmitter;
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class MRegisterInfo;
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class PassManager;
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class Pass;
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//===----------------------------------------------------------------------===//
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///
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/// TargetMachine - Primary interface to the complete machine description for
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/// the target machine. All target-specific information should be accessible
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/// through this interface.
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///
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class TargetMachine : public NonCopyableV {
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const std::string Name;
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const TargetData DataLayout; // Calculates type size & alignment
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protected:
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TargetMachine(const std::string &name, // Can only create subclasses...
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bool LittleEndian = false,
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unsigned char SubWordSize = 1, unsigned char IntRegSize = 8,
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unsigned char PtrSize = 8, unsigned char PtrAl = 8,
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unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
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unsigned char LongAl = 8, unsigned char IntAl = 4,
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unsigned char ShortAl = 2, unsigned char ByteAl = 1)
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: Name(name), DataLayout(name, LittleEndian, SubWordSize, IntRegSize,
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PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
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IntAl, ShortAl, ByteAl) {}
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public:
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virtual ~TargetMachine() {}
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const std::string &getName() const { return Name; }
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// Interfaces to the major aspects of target machine information:
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// -- Instruction opcode and operand information
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// -- Pipelines and scheduling information
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// -- Register information
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// -- Stack frame information
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// -- Cache hierarchy information
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// -- Machine-level optimization information (peephole only)
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//
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virtual const TargetInstrInfo& getInstrInfo() const = 0;
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virtual const TargetSchedInfo& getSchedInfo() const = 0;
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virtual const TargetRegInfo& getRegInfo() const = 0;
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virtual const TargetFrameInfo& getFrameInfo() const = 0;
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virtual const TargetCacheInfo& getCacheInfo() const = 0;
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virtual const TargetOptInfo& getOptInfo() const = 0;
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const TargetData &getTargetData() const { return DataLayout; }
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/// getRegisterInfo - If register information is available, return it. If
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/// not, return null. This is kept separate from RegInfo until RegInfo has
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/// details of graph coloring register allocation removed from it.
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///
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virtual const MRegisterInfo* getRegisterInfo() const { return 0; }
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// Data storage information
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//
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virtual unsigned findOptimalStorageSize(const Type* ty) const;
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this is
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/// not supported for this target.
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///
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virtual bool addPassesToJITCompile(PassManager &PM) { return true; }
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/// addPassesToEmitAssembly - Add passes to the specified pass manager to get
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/// assembly langage code emitted. Typically this will involve several steps
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/// of code generation. This method should return true if assembly emission
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/// is not supported.
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///
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virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
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return true;
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MAchineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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virtual bool addPassesToEmitMachineCode(PassManager &PM,
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MachineCodeEmitter &MCE) {
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return true;
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}
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};
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#endif
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