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https://github.com/c64scene-ar/llvm-6502.git
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d753e830cd
address to AnalyzeLoadFromClobberingLoad. This fixes a bug in load-PRE where PRE is applied to a load that is not partially redundant. <rdar://problem/16638765>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207853 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
2.8 KiB
LLVM
88 lines
2.8 KiB
LLVM
; RUN: opt -S -o - -basicaa -domtree -gvn %s | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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%struct.S1 = type { i32, i32 }
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@a2 = common global i32* null, align 8
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@a = common global i32* null, align 8
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@s1 = common global %struct.S1 zeroinitializer, align 8
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; Check that GVN doesn't determine %2 is partially redundant.
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; CHECK-LABEL: define i32 @volatile_load
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; CHECK: for.body:
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; CHECK: %2 = load i32*
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; CHECK: %3 = load volatile i32*
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; CHECK: for.cond.for.end_crit_edge:
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define i32 @volatile_load(i32 %n) {
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entry:
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%cmp6 = icmp sgt i32 %n, 0
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br i1 %cmp6, label %for.body.lr.ph, label %for.end
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for.body.lr.ph:
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%0 = load i32** @a2, align 8, !tbaa !1
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%1 = load i32** @a, align 8, !tbaa !1
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br label %for.body
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for.body:
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%indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
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%s.09 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
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%p.08 = phi i32* [ %0, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
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%2 = load i32* %p.08, align 4, !tbaa !5
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%arrayidx = getelementptr inbounds i32* %1, i64 %indvars.iv
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store i32 %2, i32* %arrayidx, align 4, !tbaa !5
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%3 = load volatile i32* %p.08, align 4, !tbaa !5
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%add = add nsw i32 %3, %s.09
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%incdec.ptr = getelementptr inbounds i32* %p.08, i64 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp ne i32 %lftr.wideiv, %n
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br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
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for.cond.for.end_crit_edge:
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%add.lcssa = phi i32 [ %add, %for.body ]
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br label %for.end
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for.end:
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%s.0.lcssa = phi i32 [ %add.lcssa, %for.cond.for.end_crit_edge ], [ 0, %entry ]
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ret i32 %s.0.lcssa
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}
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; %1 is partially redundant if %0 can be widened to a 64-bit load.
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; CHECK-LABEL: define i32 @overaligned_load
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; CHECK: if.end:
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; CHECK-NOT: %1 = load i32*
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define i32 @overaligned_load(i32 %a, i32* nocapture %b) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%0 = load i32* getelementptr inbounds (%struct.S1* @s1, i64 0, i32 0), align 8, !tbaa !5
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br label %if.end
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if.else:
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%arrayidx = getelementptr inbounds i32* %b, i64 2
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store i32 10, i32* %arrayidx, align 4, !tbaa !5
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br label %if.end
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if.end:
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%i.0 = phi i32 [ %0, %if.then ], [ 0, %if.else ]
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%p.0 = phi i32* [ getelementptr inbounds (%struct.S1* @s1, i64 0, i32 0), %if.then ], [ %b, %if.else ]
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%add.ptr = getelementptr inbounds i32* %p.0, i64 1
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%1 = load i32* %add.ptr, align 4, !tbaa !5
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%add1 = add nsw i32 %1, %i.0
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ret i32 %add1
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}
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!1 = metadata !{metadata !2, metadata !2, i64 0}
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!2 = metadata !{metadata !"any pointer", metadata !3, i64 0}
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!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
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!4 = metadata !{metadata !"Simple C/C++ TBAA"}
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!5 = metadata !{metadata !6, metadata !6, i64 0}
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!6 = metadata !{metadata !"int", metadata !3, i64 0}
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