mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-05 01:30:18 +00:00
1c7d69bbe2
Vector compare using altivec 'vcmpxxx' instructions have as third argument a vector register instead of CR one, different from integer and float-point compares. This leads to a failure in code generation, where 'SelectSETCC' expects a DAG with a CR register and gets vector register instead. This patch changes the behavior by just returning a DAG with the vector compare instruction based on the type. The patch also adds a testcase for all vector types llvm defines. It also included a fix on signed 5-bits predicates printing, where signed values were not handled correctly as signed (char are unsigned by default for PowerPC). This generates 'vspltisw' (vector splat) instruction with SIM out of range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
5.8 KiB
LLVM
192 lines
5.8 KiB
LLVM
; RUN: llc -mattr=+altivec < %s | FileCheck %s
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; Check vector comparisons using altivec.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
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%cmp = icmp eq <2 x i8> %x, %y
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%sext = sext <2 x i1> %cmp to <2 x i8>
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ret <2 x i8> %sext
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}
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; CHECK: v2si8_cmp:
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; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone {
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%cmp = icmp eq <4 x i8> %x, %y
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%sext = sext <4 x i1> %cmp to <4 x i8>
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ret <4 x i8> %sext
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}
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; CHECK: v4si8_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
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%cmp = icmp eq <8 x i8> %x, %y
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%sext = sext <8 x i1> %cmp to <8 x i8>
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ret <8 x i8> %sext
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}
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; CHECK: v8si8_cmp:
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <16 x i8> @v16si8_cmp(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
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%cmp = icmp eq <16 x i8> %x, %y
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%sext = sext <16 x i1> %cmp to <16 x i8>
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ret <16 x i8> %sext
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}
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; CHECK: v16si8_cmp:
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; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
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%cmp = icmp eq <32 x i8> %x, %y
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%sext = sext <32 x i1> %cmp to <32 x i8>
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ret <32 x i8> %sext
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}
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; CHECK: v32si8_cmp:
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; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone {
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%cmp = icmp eq <2 x i16> %x, %y
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%sext = sext <2 x i1> %cmp to <2 x i16>
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ret <2 x i16> %sext
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}
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; CHECK: v2si16_cmp:
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
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%cmp = icmp eq <4 x i16> %x, %y
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%sext = sext <4 x i1> %cmp to <4 x i16>
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ret <4 x i16> %sext
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}
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; CHECK: v4si16_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <8 x i16> @v8si16_cmp(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
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%cmp = icmp eq <8 x i16> %x, %y
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%sext = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %sext
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}
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; CHECK: v8si16_cmp:
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
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%cmp = icmp eq <16 x i16> %x, %y
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%sext = sext <16 x i1> %cmp to <16 x i16>
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ret <16 x i16> %sext
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}
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; CHECK: v16si16_cmp:
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone {
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%cmp = icmp eq <32 x i16> %x, %y
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%sext = sext <32 x i1> %cmp to <32 x i16>
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ret <32 x i16> %sext
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}
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; CHECK: v32si16_cmp:
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone {
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%cmp = icmp eq <2 x i32> %x, %y
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%sext = sext <2 x i1> %cmp to <2 x i32>
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ret <2 x i32> %sext
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}
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; CHECK: v2si32_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <4 x i32> @v4si32_cmp(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
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%cmp = icmp eq <4 x i32> %x, %y
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%sext = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %sext
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}
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; CHECK: v4si32_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
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%cmp = icmp eq <8 x i32> %x, %y
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%sext = sext <8 x i1> %cmp to <8 x i32>
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ret <8 x i32> %sext
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}
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; CHECK: v8si32_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone {
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%cmp = icmp eq <16 x i32> %x, %y
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%sext = sext <16 x i1> %cmp to <16 x i32>
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ret <16 x i32> %sext
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}
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; CHECK: v16si32_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone {
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%cmp = icmp eq <32 x i32> %x, %y
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%sext = sext <32 x i1> %cmp to <32 x i32>
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ret <32 x i32> %sext
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}
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; CHECK: v32si32_cmp:
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <2 x float> @v2f32_cmp(<2 x float> %x, <2 x float> %y) nounwind readnone {
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entry:
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%cmp = fcmp oeq <2 x float> %x, %y
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%sext = sext <2 x i1> %cmp to <2 x i32>
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%0 = bitcast <2 x i32> %sext to <2 x float>
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ret <2 x float> %0
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}
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; CHECK: v2f32_cmp:
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; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <4 x float> @v4f32_cmp(<4 x float> %x, <4 x float> %y) nounwind readnone {
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entry:
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%cmp = fcmp oeq <4 x float> %x, %y
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%0 = bitcast <4 x i32> %sext to <4 x float>
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ret <4 x float> %0
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}
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; CHECK: v4f32_cmp:
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; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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define <8 x float> @v8f32_cmp(<8 x float> %x, <8 x float> %y) nounwind readnone {
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entry:
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%cmp = fcmp oeq <8 x float> %x, %y
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%sext = sext <8 x i1> %cmp to <8 x i32>
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%0 = bitcast <8 x i32> %sext to <8 x float>
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ret <8 x float> %0
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}
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; CHECK: v8f32_cmp:
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; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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