Saleem Abdulrasool 6c2be4ff95 ARM: try harder to detect non-IT eligible instructions ... For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215382 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-11 20:13:25 +00:00
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Analysis
AsmParser
Bitcode
CodeGen	PeepholeOptimizer: make parameter ref to SmallPtrSetImpl	2014-08-11 13:52:46 +00:00
DebugInfo
ExecutionEngine
IR	Fix typos:	2014-08-11 18:04:46 +00:00
IRReader
LineEditor
Linker	Fix use of uninitialized variable.	2014-08-11 17:07:34 +00:00
LTO
MC	MC: Diagnose an unexpected token in COFF .section instead of asserting	2014-08-11 18:34:43 +00:00
Object
Option
ProfileData
Support
TableGen
Target	ARM: try harder to detect non-IT eligible instructions	2014-08-11 20:13:25 +00:00
Transforms
CMakeLists.txt
LLVMBuild.txt
Makefile