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2debd48ca7
The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144503 91177308-0d34-0410-b5e6-96231b3b80d8
831 lines
32 KiB
C++
831 lines
32 KiB
C++
//===- StrongPHIElimination.cpp - Eliminate PHI nodes by inserting copies -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass eliminates PHI instructions by aggressively coalescing the copies
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// that would be inserted by a naive algorithm and only inserting the copies
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// that are necessary. The coalescing technique initially assumes that all
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// registers appearing in a PHI instruction do not interfere. It then eliminates
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// proven interferences, using dominators to only perform a linear number of
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// interference tests instead of the quadratic number of interference tests
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// that this would naively require. This is a technique derived from:
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//
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// Budimlic, et al. Fast copy coalescing and live-range identification.
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// In Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language
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// Design and Implementation (Berlin, Germany, June 17 - 19, 2002).
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// PLDI '02. ACM, New York, NY, 25-32.
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//
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// The original implementation constructs a data structure they call a dominance
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// forest for this purpose. The dominance forest was shown to be unnecessary,
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// as it is possible to emulate the creation and traversal of a dominance forest
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// by directly using the dominator tree, rather than actually constructing the
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// dominance forest. This technique is explained in:
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//
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// Boissinot, et al. Revisiting Out-of-SSA Translation for Correctness, Code
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// Quality and Efficiency,
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// In Proceedings of the 7th annual IEEE/ACM International Symposium on Code
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// Generation and Optimization (Seattle, Washington, March 22 - 25, 2009).
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// CGO '09. IEEE, Washington, DC, 114-125.
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//
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// Careful implementation allows for all of the dominator forest interference
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// checks to be performed at once in a single depth-first traversal of the
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// dominator tree, which is what is implemented here.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "strongphielim"
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#include "PHIEliminationUtils.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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namespace {
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class StrongPHIElimination : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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StrongPHIElimination() : MachineFunctionPass(ID) {
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initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
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}
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virtual void getAnalysisUsage(AnalysisUsage&) const;
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bool runOnMachineFunction(MachineFunction&);
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private:
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/// This struct represents a single node in the union-find data structure
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/// representing the variable congruence classes. There is one difference
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/// from a normal union-find data structure. We steal two bits from the parent
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/// pointer . One of these bits is used to represent whether the register
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/// itself has been isolated, and the other is used to represent whether the
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/// PHI with that register as its destination has been isolated.
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///
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/// Note that this leads to the strange situation where the leader of a
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/// congruence class may no longer logically be a member, due to being
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/// isolated.
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struct Node {
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enum Flags {
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kRegisterIsolatedFlag = 1,
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kPHIIsolatedFlag = 2
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};
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Node(unsigned v) : value(v), rank(0) { parent.setPointer(this); }
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Node *getLeader();
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PointerIntPair<Node*, 2> parent;
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unsigned value;
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unsigned rank;
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};
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/// Add a register in a new congruence class containing only itself.
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void addReg(unsigned);
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/// Join the congruence classes of two registers. This function is biased
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/// towards the left argument, i.e. after
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///
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/// addReg(r2);
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/// unionRegs(r1, r2);
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///
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/// the leader of the unioned congruence class is the same as the leader of
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/// r1's congruence class prior to the union. This is actually relied upon
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/// in the copy insertion code.
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void unionRegs(unsigned, unsigned);
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/// Get the color of a register. The color is 0 if the register has been
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/// isolated.
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unsigned getRegColor(unsigned);
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// Isolate a register.
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void isolateReg(unsigned);
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/// Get the color of a PHI. The color of a PHI is 0 if the PHI has been
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/// isolated. Otherwise, it is the original color of its destination and
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/// all of its operands (before they were isolated, if they were).
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unsigned getPHIColor(MachineInstr*);
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/// Isolate a PHI.
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void isolatePHI(MachineInstr*);
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/// Traverses a basic block, splitting any interferences found between
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/// registers in the same congruence class. It takes two DenseMaps as
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/// arguments that it also updates: CurrentDominatingParent, which maps
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/// a color to the register in that congruence class whose definition was
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/// most recently seen, and ImmediateDominatingParent, which maps a register
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/// to the register in the same congruence class that most immediately
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/// dominates it.
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///
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/// This function assumes that it is being called in a depth-first traversal
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/// of the dominator tree.
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void SplitInterferencesForBasicBlock(
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MachineBasicBlock&,
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DenseMap<unsigned, unsigned> &CurrentDominatingParent,
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DenseMap<unsigned, unsigned> &ImmediateDominatingParent);
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// Lowers a PHI instruction, inserting copies of the source and destination
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// registers as necessary.
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void InsertCopiesForPHI(MachineInstr*, MachineBasicBlock*);
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// Merges the live interval of Reg into NewReg and renames Reg to NewReg
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// everywhere that Reg appears. Requires Reg and NewReg to have non-
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// overlapping lifetimes.
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void MergeLIsAndRename(unsigned Reg, unsigned NewReg);
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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MachineDominatorTree *DT;
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LiveIntervals *LI;
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BumpPtrAllocator Allocator;
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DenseMap<unsigned, Node*> RegNodeMap;
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// Maps a basic block to a list of its defs of registers that appear as PHI
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// sources.
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DenseMap<MachineBasicBlock*, std::vector<MachineInstr*> > PHISrcDefs;
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// Maps a color to a pair of a MachineInstr* and a virtual register, which
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// is the operand of that PHI corresponding to the current basic block.
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DenseMap<unsigned, std::pair<MachineInstr*, unsigned> > CurrentPHIForColor;
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// FIXME: Can these two data structures be combined? Would a std::multimap
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// be any better?
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// Stores pairs of predecessor basic blocks and the source registers of
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// inserted copy instructions.
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typedef DenseSet<std::pair<MachineBasicBlock*, unsigned> > SrcCopySet;
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SrcCopySet InsertedSrcCopySet;
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// Maps pairs of predecessor basic blocks and colors to their defining copy
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// instructions.
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typedef DenseMap<std::pair<MachineBasicBlock*, unsigned>, MachineInstr*>
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SrcCopyMap;
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SrcCopyMap InsertedSrcCopyMap;
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// Maps inserted destination copy registers to their defining copy
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// instructions.
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typedef DenseMap<unsigned, MachineInstr*> DestCopyMap;
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DestCopyMap InsertedDestCopies;
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};
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struct MIIndexCompare {
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MIIndexCompare(LiveIntervals *LiveIntervals) : LI(LiveIntervals) { }
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bool operator()(const MachineInstr *LHS, const MachineInstr *RHS) const {
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return LI->getInstructionIndex(LHS) < LI->getInstructionIndex(RHS);
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}
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LiveIntervals *LI;
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};
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} // namespace
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STATISTIC(NumPHIsLowered, "Number of PHIs lowered");
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STATISTIC(NumDestCopiesInserted, "Number of destination copies inserted");
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STATISTIC(NumSrcCopiesInserted, "Number of source copies inserted");
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char StrongPHIElimination::ID = 0;
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INITIALIZE_PASS_BEGIN(StrongPHIElimination, "strong-phi-node-elimination",
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"Eliminate PHI nodes for register allocation, intelligently", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(StrongPHIElimination, "strong-phi-node-elimination",
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"Eliminate PHI nodes for register allocation, intelligently", false, false)
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char &llvm::StrongPHIEliminationID = StrongPHIElimination::ID;
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void StrongPHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<SlotIndexes>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static MachineOperand *findLastUse(MachineBasicBlock *MBB, unsigned Reg) {
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// FIXME: This only needs to check from the first terminator, as only the
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// first terminator can use a virtual register.
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for (MachineBasicBlock::reverse_iterator RI = MBB->rbegin(); ; ++RI) {
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assert (RI != MBB->rend());
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MachineInstr *MI = &*RI;
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for (MachineInstr::mop_iterator OI = MI->operands_begin(),
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OE = MI->operands_end(); OI != OE; ++OI) {
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MachineOperand &MO = *OI;
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if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
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return &MO;
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}
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}
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return NULL;
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}
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bool StrongPHIElimination::runOnMachineFunction(MachineFunction &MF) {
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MRI = &MF.getRegInfo();
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TII = MF.getTarget().getInstrInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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LI = &getAnalysis<LiveIntervals>();
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for (MachineFunction::iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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for (MachineBasicBlock::iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->isPHI(); ++BBI) {
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unsigned DestReg = BBI->getOperand(0).getReg();
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addReg(DestReg);
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PHISrcDefs[I].push_back(BBI);
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for (unsigned i = 1; i < BBI->getNumOperands(); i += 2) {
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MachineOperand &SrcMO = BBI->getOperand(i);
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unsigned SrcReg = SrcMO.getReg();
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addReg(SrcReg);
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unionRegs(DestReg, SrcReg);
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MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
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if (DefMI)
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PHISrcDefs[DefMI->getParent()].push_back(DefMI);
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}
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}
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}
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// Perform a depth-first traversal of the dominator tree, splitting
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// interferences amongst PHI-congruence classes.
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DenseMap<unsigned, unsigned> CurrentDominatingParent;
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DenseMap<unsigned, unsigned> ImmediateDominatingParent;
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for (df_iterator<MachineDomTreeNode*> DI = df_begin(DT->getRootNode()),
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DE = df_end(DT->getRootNode()); DI != DE; ++DI) {
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SplitInterferencesForBasicBlock(*DI->getBlock(),
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CurrentDominatingParent,
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ImmediateDominatingParent);
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}
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// Insert copies for all PHI source and destination registers.
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for (MachineFunction::iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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for (MachineBasicBlock::iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->isPHI(); ++BBI) {
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InsertCopiesForPHI(BBI, I);
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}
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}
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// FIXME: Preserve the equivalence classes during copy insertion and use
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// the preversed equivalence classes instead of recomputing them.
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RegNodeMap.clear();
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for (MachineFunction::iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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for (MachineBasicBlock::iterator BBI = I->begin(), BBE = I->end();
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BBI != BBE && BBI->isPHI(); ++BBI) {
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unsigned DestReg = BBI->getOperand(0).getReg();
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addReg(DestReg);
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for (unsigned i = 1; i < BBI->getNumOperands(); i += 2) {
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unsigned SrcReg = BBI->getOperand(i).getReg();
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addReg(SrcReg);
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unionRegs(DestReg, SrcReg);
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}
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}
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}
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DenseMap<unsigned, unsigned> RegRenamingMap;
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bool Changed = false;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end();
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I != E; ++I) {
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MachineBasicBlock::iterator BBI = I->begin(), BBE = I->end();
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while (BBI != BBE && BBI->isPHI()) {
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MachineInstr *PHI = BBI;
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assert(PHI->getNumOperands() > 0);
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unsigned SrcReg = PHI->getOperand(1).getReg();
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unsigned SrcColor = getRegColor(SrcReg);
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unsigned NewReg = RegRenamingMap[SrcColor];
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if (!NewReg) {
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NewReg = SrcReg;
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RegRenamingMap[SrcColor] = SrcReg;
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}
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MergeLIsAndRename(SrcReg, NewReg);
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unsigned DestReg = PHI->getOperand(0).getReg();
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if (!InsertedDestCopies.count(DestReg))
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MergeLIsAndRename(DestReg, NewReg);
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for (unsigned i = 3; i < PHI->getNumOperands(); i += 2) {
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unsigned SrcReg = PHI->getOperand(i).getReg();
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MergeLIsAndRename(SrcReg, NewReg);
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}
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++BBI;
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LI->RemoveMachineInstrFromMaps(PHI);
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PHI->eraseFromParent();
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Changed = true;
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}
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}
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// Due to the insertion of copies to split live ranges, the live intervals are
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// guaranteed to not overlap, except in one case: an original PHI source and a
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// PHI destination copy. In this case, they have the same value and thus don't
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// truly intersect, so we merge them into the value live at that point.
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// FIXME: Is there some better way we can handle this?
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for (DestCopyMap::iterator I = InsertedDestCopies.begin(),
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E = InsertedDestCopies.end(); I != E; ++I) {
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unsigned DestReg = I->first;
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unsigned DestColor = getRegColor(DestReg);
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unsigned NewReg = RegRenamingMap[DestColor];
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LiveInterval &DestLI = LI->getInterval(DestReg);
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LiveInterval &NewLI = LI->getInterval(NewReg);
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assert(DestLI.ranges.size() == 1
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&& "PHI destination copy's live interval should be a single live "
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"range from the beginning of the BB to the copy instruction.");
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LiveRange *DestLR = DestLI.begin();
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VNInfo *NewVNI = NewLI.getVNInfoAt(DestLR->start);
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if (!NewVNI) {
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NewVNI = NewLI.createValueCopy(DestLR->valno, LI->getVNInfoAllocator());
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MachineInstr *CopyInstr = I->second;
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CopyInstr->getOperand(1).setIsKill(true);
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}
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LiveRange NewLR(DestLR->start, DestLR->end, NewVNI);
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NewLI.addRange(NewLR);
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LI->removeInterval(DestReg);
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MRI->replaceRegWith(DestReg, NewReg);
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}
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// Adjust the live intervals of all PHI source registers to handle the case
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// where the PHIs in successor blocks were the only later uses of the source
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// register.
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for (SrcCopySet::iterator I = InsertedSrcCopySet.begin(),
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E = InsertedSrcCopySet.end(); I != E; ++I) {
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MachineBasicBlock *MBB = I->first;
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unsigned SrcReg = I->second;
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if (unsigned RenamedRegister = RegRenamingMap[getRegColor(SrcReg)])
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SrcReg = RenamedRegister;
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LiveInterval &SrcLI = LI->getInterval(SrcReg);
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bool isLiveOut = false;
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI) {
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if (SrcLI.liveAt(LI->getMBBStartIdx(*SI))) {
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isLiveOut = true;
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break;
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}
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}
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if (isLiveOut)
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continue;
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MachineOperand *LastUse = findLastUse(MBB, SrcReg);
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assert(LastUse);
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SlotIndex LastUseIndex = LI->getInstructionIndex(LastUse->getParent());
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SrcLI.removeRange(LastUseIndex.getRegSlot(), LI->getMBBEndIdx(MBB));
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LastUse->setIsKill(true);
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}
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LI->renumber();
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Allocator.Reset();
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RegNodeMap.clear();
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PHISrcDefs.clear();
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InsertedSrcCopySet.clear();
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InsertedSrcCopyMap.clear();
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InsertedDestCopies.clear();
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return Changed;
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}
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void StrongPHIElimination::addReg(unsigned Reg) {
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if (RegNodeMap.count(Reg))
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return;
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RegNodeMap[Reg] = new (Allocator) Node(Reg);
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}
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StrongPHIElimination::Node*
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StrongPHIElimination::Node::getLeader() {
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Node *N = this;
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Node *Parent = parent.getPointer();
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Node *Grandparent = Parent->parent.getPointer();
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while (Parent != Grandparent) {
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N->parent.setPointer(Grandparent);
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N = Grandparent;
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Parent = Parent->parent.getPointer();
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Grandparent = Parent->parent.getPointer();
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}
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return Parent;
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}
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unsigned StrongPHIElimination::getRegColor(unsigned Reg) {
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DenseMap<unsigned, Node*>::iterator RI = RegNodeMap.find(Reg);
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if (RI == RegNodeMap.end())
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return 0;
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Node *Node = RI->second;
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if (Node->parent.getInt() & Node::kRegisterIsolatedFlag)
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return 0;
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return Node->getLeader()->value;
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}
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void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) {
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Node *Node1 = RegNodeMap[Reg1]->getLeader();
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Node *Node2 = RegNodeMap[Reg2]->getLeader();
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if (Node1->rank > Node2->rank) {
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Node2->parent.setPointer(Node1->getLeader());
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} else if (Node1->rank < Node2->rank) {
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Node1->parent.setPointer(Node2->getLeader());
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} else if (Node1 != Node2) {
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Node2->parent.setPointer(Node1->getLeader());
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Node1->rank++;
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}
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}
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void StrongPHIElimination::isolateReg(unsigned Reg) {
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Node *Node = RegNodeMap[Reg];
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Node->parent.setInt(Node->parent.getInt() | Node::kRegisterIsolatedFlag);
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}
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unsigned StrongPHIElimination::getPHIColor(MachineInstr *PHI) {
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assert(PHI->isPHI());
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unsigned DestReg = PHI->getOperand(0).getReg();
|
|
Node *DestNode = RegNodeMap[DestReg];
|
|
if (DestNode->parent.getInt() & Node::kPHIIsolatedFlag)
|
|
return 0;
|
|
|
|
for (unsigned i = 1; i < PHI->getNumOperands(); i += 2) {
|
|
unsigned SrcColor = getRegColor(PHI->getOperand(i).getReg());
|
|
if (SrcColor)
|
|
return SrcColor;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void StrongPHIElimination::isolatePHI(MachineInstr *PHI) {
|
|
assert(PHI->isPHI());
|
|
Node *Node = RegNodeMap[PHI->getOperand(0).getReg()];
|
|
Node->parent.setInt(Node->parent.getInt() | Node::kPHIIsolatedFlag);
|
|
}
|
|
|
|
/// SplitInterferencesForBasicBlock - traverses a basic block, splitting any
|
|
/// interferences found between registers in the same congruence class. It
|
|
/// takes two DenseMaps as arguments that it also updates:
|
|
///
|
|
/// 1) CurrentDominatingParent, which maps a color to the register in that
|
|
/// congruence class whose definition was most recently seen.
|
|
///
|
|
/// 2) ImmediateDominatingParent, which maps a register to the register in the
|
|
/// same congruence class that most immediately dominates it.
|
|
///
|
|
/// This function assumes that it is being called in a depth-first traversal
|
|
/// of the dominator tree.
|
|
///
|
|
/// The algorithm used here is a generalization of the dominance-based SSA test
|
|
/// for two variables. If there are variables a_1, ..., a_n such that
|
|
///
|
|
/// def(a_1) dom ... dom def(a_n),
|
|
///
|
|
/// then we can test for an interference between any two a_i by only using O(n)
|
|
/// interference tests between pairs of variables. If i < j and a_i and a_j
|
|
/// interfere, then a_i is alive at def(a_j), so it is also alive at def(a_i+1).
|
|
/// Thus, in order to test for an interference involving a_i, we need only check
|
|
/// for a potential interference with a_i+1.
|
|
///
|
|
/// This method can be generalized to arbitrary sets of variables by performing
|
|
/// a depth-first traversal of the dominator tree. As we traverse down a branch
|
|
/// of the dominator tree, we keep track of the current dominating variable and
|
|
/// only perform an interference test with that variable. However, when we go to
|
|
/// another branch of the dominator tree, the definition of the current dominating
|
|
/// variable may no longer dominate the current block. In order to correct this,
|
|
/// we need to use a stack of past choices of the current dominating variable
|
|
/// and pop from this stack until we find a variable whose definition actually
|
|
/// dominates the current block.
|
|
///
|
|
/// There will be one push on this stack for each variable that has become the
|
|
/// current dominating variable, so instead of using an explicit stack we can
|
|
/// simply associate the previous choice for a current dominating variable with
|
|
/// the new choice. This works better in our implementation, where we test for
|
|
/// interference in multiple distinct sets at once.
|
|
void
|
|
StrongPHIElimination::SplitInterferencesForBasicBlock(
|
|
MachineBasicBlock &MBB,
|
|
DenseMap<unsigned, unsigned> &CurrentDominatingParent,
|
|
DenseMap<unsigned, unsigned> &ImmediateDominatingParent) {
|
|
// Sort defs by their order in the original basic block, as the code below
|
|
// assumes that it is processing definitions in dominance order.
|
|
std::vector<MachineInstr*> &DefInstrs = PHISrcDefs[&MBB];
|
|
std::sort(DefInstrs.begin(), DefInstrs.end(), MIIndexCompare(LI));
|
|
|
|
for (std::vector<MachineInstr*>::const_iterator BBI = DefInstrs.begin(),
|
|
BBE = DefInstrs.end(); BBI != BBE; ++BBI) {
|
|
for (MachineInstr::const_mop_iterator I = (*BBI)->operands_begin(),
|
|
E = (*BBI)->operands_end(); I != E; ++I) {
|
|
const MachineOperand &MO = *I;
|
|
|
|
// FIXME: This would be faster if it were possible to bail out of checking
|
|
// an instruction's operands after the explicit defs, but this is incorrect
|
|
// for variadic instructions, which may appear before register allocation
|
|
// in the future.
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
|
|
unsigned DestReg = MO.getReg();
|
|
if (!DestReg || !TargetRegisterInfo::isVirtualRegister(DestReg))
|
|
continue;
|
|
|
|
// If the virtual register being defined is not used in any PHI or has
|
|
// already been isolated, then there are no more interferences to check.
|
|
unsigned DestColor = getRegColor(DestReg);
|
|
if (!DestColor)
|
|
continue;
|
|
|
|
// The input to this pass sometimes is not in SSA form in every basic
|
|
// block, as some virtual registers have redefinitions. We could eliminate
|
|
// this by fixing the passes that generate the non-SSA code, or we could
|
|
// handle it here by tracking defining machine instructions rather than
|
|
// virtual registers. For now, we just handle the situation conservatively
|
|
// in a way that will possibly lead to false interferences.
|
|
unsigned &CurrentParent = CurrentDominatingParent[DestColor];
|
|
unsigned NewParent = CurrentParent;
|
|
if (NewParent == DestReg)
|
|
continue;
|
|
|
|
// Pop registers from the stack represented by ImmediateDominatingParent
|
|
// until we find a parent that dominates the current instruction.
|
|
while (NewParent && (!DT->dominates(MRI->getVRegDef(NewParent), *BBI)
|
|
|| !getRegColor(NewParent)))
|
|
NewParent = ImmediateDominatingParent[NewParent];
|
|
|
|
// If NewParent is nonzero, then its definition dominates the current
|
|
// instruction, so it is only necessary to check for the liveness of
|
|
// NewParent in order to check for an interference.
|
|
if (NewParent
|
|
&& LI->getInterval(NewParent).liveAt(LI->getInstructionIndex(*BBI))) {
|
|
// If there is an interference, always isolate the new register. This
|
|
// could be improved by using a heuristic that decides which of the two
|
|
// registers to isolate.
|
|
isolateReg(DestReg);
|
|
CurrentParent = NewParent;
|
|
} else {
|
|
// If there is no interference, update ImmediateDominatingParent and set
|
|
// the CurrentDominatingParent for this color to the current register.
|
|
ImmediateDominatingParent[DestReg] = NewParent;
|
|
CurrentParent = DestReg;
|
|
}
|
|
}
|
|
}
|
|
|
|
// We now walk the PHIs in successor blocks and check for interferences. This
|
|
// is necessary because the use of a PHI's operands are logically contained in
|
|
// the predecessor block. The def of a PHI's destination register is processed
|
|
// along with the other defs in a basic block.
|
|
|
|
CurrentPHIForColor.clear();
|
|
|
|
for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
|
|
SE = MBB.succ_end(); SI != SE; ++SI) {
|
|
for (MachineBasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
|
|
BBI != BBE && BBI->isPHI(); ++BBI) {
|
|
MachineInstr *PHI = BBI;
|
|
|
|
// If a PHI is already isolated, either by being isolated directly or
|
|
// having all of its operands isolated, ignore it.
|
|
unsigned Color = getPHIColor(PHI);
|
|
if (!Color)
|
|
continue;
|
|
|
|
// Find the index of the PHI operand that corresponds to this basic block.
|
|
unsigned PredIndex;
|
|
for (PredIndex = 1; PredIndex < PHI->getNumOperands(); PredIndex += 2) {
|
|
if (PHI->getOperand(PredIndex + 1).getMBB() == &MBB)
|
|
break;
|
|
}
|
|
assert(PredIndex < PHI->getNumOperands());
|
|
unsigned PredOperandReg = PHI->getOperand(PredIndex).getReg();
|
|
|
|
// Pop registers from the stack represented by ImmediateDominatingParent
|
|
// until we find a parent that dominates the current instruction.
|
|
unsigned &CurrentParent = CurrentDominatingParent[Color];
|
|
unsigned NewParent = CurrentParent;
|
|
while (NewParent
|
|
&& (!DT->dominates(MRI->getVRegDef(NewParent)->getParent(), &MBB)
|
|
|| !getRegColor(NewParent)))
|
|
NewParent = ImmediateDominatingParent[NewParent];
|
|
CurrentParent = NewParent;
|
|
|
|
// If there is an interference with a register, always isolate the
|
|
// register rather than the PHI. It is also possible to isolate the
|
|
// PHI, but that introduces copies for all of the registers involved
|
|
// in that PHI.
|
|
if (NewParent && LI->isLiveOutOfMBB(LI->getInterval(NewParent), &MBB)
|
|
&& NewParent != PredOperandReg)
|
|
isolateReg(NewParent);
|
|
|
|
std::pair<MachineInstr*, unsigned>
|
|
&CurrentPHI = CurrentPHIForColor[Color];
|
|
|
|
// If two PHIs have the same operand from every shared predecessor, then
|
|
// they don't actually interfere. Otherwise, isolate the current PHI. This
|
|
// could possibly be improved, e.g. we could isolate the PHI with the
|
|
// fewest operands.
|
|
if (CurrentPHI.first && CurrentPHI.second != PredOperandReg)
|
|
isolatePHI(PHI);
|
|
else
|
|
CurrentPHI = std::make_pair(PHI, PredOperandReg);
|
|
}
|
|
}
|
|
}
|
|
|
|
void StrongPHIElimination::InsertCopiesForPHI(MachineInstr *PHI,
|
|
MachineBasicBlock *MBB) {
|
|
assert(PHI->isPHI());
|
|
++NumPHIsLowered;
|
|
unsigned PHIColor = getPHIColor(PHI);
|
|
|
|
for (unsigned i = 1; i < PHI->getNumOperands(); i += 2) {
|
|
MachineOperand &SrcMO = PHI->getOperand(i);
|
|
|
|
// If a source is defined by an implicit def, there is no need to insert a
|
|
// copy in the predecessor.
|
|
if (SrcMO.isUndef())
|
|
continue;
|
|
|
|
unsigned SrcReg = SrcMO.getReg();
|
|
assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
|
|
"Machine PHI Operands must all be virtual registers!");
|
|
|
|
MachineBasicBlock *PredBB = PHI->getOperand(i + 1).getMBB();
|
|
unsigned SrcColor = getRegColor(SrcReg);
|
|
|
|
// If neither the PHI nor the operand were isolated, then we only need to
|
|
// set the phi-kill flag on the VNInfo at this PHI.
|
|
if (PHIColor && SrcColor == PHIColor) {
|
|
LiveInterval &SrcInterval = LI->getInterval(SrcReg);
|
|
SlotIndex PredIndex = LI->getMBBEndIdx(PredBB);
|
|
VNInfo *SrcVNI = SrcInterval.getVNInfoBefore(PredIndex);
|
|
assert(SrcVNI);
|
|
SrcVNI->setHasPHIKill(true);
|
|
continue;
|
|
}
|
|
|
|
unsigned CopyReg = 0;
|
|
if (PHIColor) {
|
|
SrcCopyMap::const_iterator I
|
|
= InsertedSrcCopyMap.find(std::make_pair(PredBB, PHIColor));
|
|
CopyReg
|
|
= I != InsertedSrcCopyMap.end() ? I->second->getOperand(0).getReg() : 0;
|
|
}
|
|
|
|
if (!CopyReg) {
|
|
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
|
|
CopyReg = MRI->createVirtualRegister(RC);
|
|
|
|
MachineBasicBlock::iterator
|
|
CopyInsertPoint = findPHICopyInsertPoint(PredBB, MBB, SrcReg);
|
|
unsigned SrcSubReg = SrcMO.getSubReg();
|
|
MachineInstr *CopyInstr = BuildMI(*PredBB,
|
|
CopyInsertPoint,
|
|
PHI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY),
|
|
CopyReg).addReg(SrcReg, 0, SrcSubReg);
|
|
LI->InsertMachineInstrInMaps(CopyInstr);
|
|
++NumSrcCopiesInserted;
|
|
|
|
// addLiveRangeToEndOfBlock() also adds the phikill flag to the VNInfo for
|
|
// the newly added range.
|
|
LI->addLiveRangeToEndOfBlock(CopyReg, CopyInstr);
|
|
InsertedSrcCopySet.insert(std::make_pair(PredBB, SrcReg));
|
|
|
|
addReg(CopyReg);
|
|
if (PHIColor) {
|
|
unionRegs(PHIColor, CopyReg);
|
|
assert(getRegColor(CopyReg) != CopyReg);
|
|
} else {
|
|
PHIColor = CopyReg;
|
|
assert(getRegColor(CopyReg) == CopyReg);
|
|
}
|
|
|
|
if (!InsertedSrcCopyMap.count(std::make_pair(PredBB, PHIColor)))
|
|
InsertedSrcCopyMap[std::make_pair(PredBB, PHIColor)] = CopyInstr;
|
|
}
|
|
|
|
SrcMO.setReg(CopyReg);
|
|
|
|
// If SrcReg is not live beyond the PHI, trim its interval so that it is no
|
|
// longer live-in to MBB. Note that SrcReg may appear in other PHIs that are
|
|
// processed later, but this is still correct to do at this point because we
|
|
// never rely on LiveIntervals being correct while inserting copies.
|
|
// FIXME: Should this just count uses at PHIs like the normal PHIElimination
|
|
// pass does?
|
|
LiveInterval &SrcLI = LI->getInterval(SrcReg);
|
|
SlotIndex MBBStartIndex = LI->getMBBStartIdx(MBB);
|
|
SlotIndex PHIIndex = LI->getInstructionIndex(PHI);
|
|
SlotIndex NextInstrIndex = PHIIndex.getNextIndex();
|
|
if (SrcLI.liveAt(MBBStartIndex) && SrcLI.expiredAt(NextInstrIndex))
|
|
SrcLI.removeRange(MBBStartIndex, PHIIndex, true);
|
|
}
|
|
|
|
unsigned DestReg = PHI->getOperand(0).getReg();
|
|
unsigned DestColor = getRegColor(DestReg);
|
|
|
|
if (PHIColor && DestColor == PHIColor) {
|
|
LiveInterval &DestLI = LI->getInterval(DestReg);
|
|
|
|
// Set the phi-def flag for the VN at this PHI.
|
|
SlotIndex PHIIndex = LI->getInstructionIndex(PHI);
|
|
VNInfo *DestVNI = DestLI.getVNInfoAt(PHIIndex.getRegSlot());
|
|
assert(DestVNI);
|
|
DestVNI->setIsPHIDef(true);
|
|
|
|
// Prior to PHI elimination, the live ranges of PHIs begin at their defining
|
|
// instruction. After PHI elimination, PHI instructions are replaced by VNs
|
|
// with the phi-def flag set, and the live ranges of these VNs start at the
|
|
// beginning of the basic block.
|
|
SlotIndex MBBStartIndex = LI->getMBBStartIdx(MBB);
|
|
DestVNI->def = MBBStartIndex;
|
|
DestLI.addRange(LiveRange(MBBStartIndex,
|
|
PHIIndex.getRegSlot(),
|
|
DestVNI));
|
|
return;
|
|
}
|
|
|
|
const TargetRegisterClass *RC = MRI->getRegClass(DestReg);
|
|
unsigned CopyReg = MRI->createVirtualRegister(RC);
|
|
|
|
MachineInstr *CopyInstr = BuildMI(*MBB,
|
|
MBB->SkipPHIsAndLabels(MBB->begin()),
|
|
PHI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY),
|
|
DestReg).addReg(CopyReg);
|
|
LI->InsertMachineInstrInMaps(CopyInstr);
|
|
PHI->getOperand(0).setReg(CopyReg);
|
|
++NumDestCopiesInserted;
|
|
|
|
// Add the region from the beginning of MBB to the copy instruction to
|
|
// CopyReg's live interval, and give the VNInfo the phidef flag.
|
|
LiveInterval &CopyLI = LI->getOrCreateInterval(CopyReg);
|
|
SlotIndex MBBStartIndex = LI->getMBBStartIdx(MBB);
|
|
SlotIndex DestCopyIndex = LI->getInstructionIndex(CopyInstr);
|
|
VNInfo *CopyVNI = CopyLI.getNextValue(MBBStartIndex,
|
|
CopyInstr,
|
|
LI->getVNInfoAllocator());
|
|
CopyVNI->setIsPHIDef(true);
|
|
CopyLI.addRange(LiveRange(MBBStartIndex,
|
|
DestCopyIndex.getRegSlot(),
|
|
CopyVNI));
|
|
|
|
// Adjust DestReg's live interval to adjust for its new definition at
|
|
// CopyInstr.
|
|
LiveInterval &DestLI = LI->getOrCreateInterval(DestReg);
|
|
SlotIndex PHIIndex = LI->getInstructionIndex(PHI);
|
|
DestLI.removeRange(PHIIndex.getRegSlot(), DestCopyIndex.getRegSlot());
|
|
|
|
VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
|
|
assert(DestVNI);
|
|
DestVNI->def = DestCopyIndex.getRegSlot();
|
|
|
|
InsertedDestCopies[CopyReg] = CopyInstr;
|
|
}
|
|
|
|
void StrongPHIElimination::MergeLIsAndRename(unsigned Reg, unsigned NewReg) {
|
|
if (Reg == NewReg)
|
|
return;
|
|
|
|
LiveInterval &OldLI = LI->getInterval(Reg);
|
|
LiveInterval &NewLI = LI->getInterval(NewReg);
|
|
|
|
// Merge the live ranges of the two registers.
|
|
DenseMap<VNInfo*, VNInfo*> VNMap;
|
|
for (LiveInterval::iterator LRI = OldLI.begin(), LRE = OldLI.end();
|
|
LRI != LRE; ++LRI) {
|
|
LiveRange OldLR = *LRI;
|
|
VNInfo *OldVN = OldLR.valno;
|
|
|
|
VNInfo *&NewVN = VNMap[OldVN];
|
|
if (!NewVN) {
|
|
NewVN = NewLI.createValueCopy(OldVN, LI->getVNInfoAllocator());
|
|
VNMap[OldVN] = NewVN;
|
|
}
|
|
|
|
LiveRange LR(OldLR.start, OldLR.end, NewVN);
|
|
NewLI.addRange(LR);
|
|
}
|
|
|
|
// Remove the LiveInterval for the register being renamed and replace all
|
|
// of its defs and uses with the new register.
|
|
LI->removeInterval(Reg);
|
|
MRI->replaceRegWith(Reg, NewReg);
|
|
}
|