mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-24 23:29:41 +00:00
6c2cf8b1fb
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
484 lines
16 KiB
C++
484 lines
16 KiB
C++
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "InstPrinter/MipsInstPrinter.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/ADT/STLExtras.h"
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#define GET_INSTRINFO_CTOR
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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: MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
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RI(*TM.getSubtargetImpl(), *this),
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UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
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const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
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return RI;
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}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
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(Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
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(Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
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(Opc == Mips::LDC164_P8)) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
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(Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
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(Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
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(Opc == Mips::SDC164_P8)) {
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if ((MI->getOperand(1).isFI()) && // is a stack slot
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(MI->getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(2)))) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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DebugLoc DL;
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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}
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void MipsInstrInfo::
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copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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unsigned Opc = 0, ZeroReg = 0;
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if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
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else if (Mips::CCRRegClass.contains(SrcReg))
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Opc = Mips::CFC1;
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else if (Mips::FGR32RegClass.contains(SrcReg))
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Opc = Mips::MFC1;
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else if (SrcReg == Mips::HI)
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Opc = Mips::MFHI, SrcReg = 0;
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else if (SrcReg == Mips::LO)
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Opc = Mips::MFLO, SrcReg = 0;
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}
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else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
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if (Mips::CCRRegClass.contains(DestReg))
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Opc = Mips::CTC1;
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else if (Mips::FGR32RegClass.contains(DestReg))
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Opc = Mips::MTC1;
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else if (DestReg == Mips::HI)
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Opc = Mips::MTHI, DestReg = 0;
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else if (DestReg == Mips::LO)
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Opc = Mips::MTLO, DestReg = 0;
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}
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else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_S;
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else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D32;
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else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
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Opc = Mips::FMOV_D64;
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else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
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Opc = Mips::MOVCCRToCCR;
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else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::CPU64RegsRegClass.contains(SrcReg))
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Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
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else if (SrcReg == Mips::HI64)
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Opc = Mips::MFHI64, SrcReg = 0;
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else if (SrcReg == Mips::LO64)
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Opc = Mips::MFLO64, SrcReg = 0;
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else if (Mips::FGR64RegClass.contains(SrcReg))
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Opc = Mips::DMFC1;
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}
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else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
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if (DestReg == Mips::HI64)
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Opc = Mips::MTHI64, DestReg = 0;
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else if (DestReg == Mips::LO64)
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Opc = Mips::MTLO64, DestReg = 0;
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else if (Mips::FGR64RegClass.contains(DestReg))
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Opc = Mips::DMTC1;
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}
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assert(Opc && "Cannot copy registers");
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MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
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if (DestReg)
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MIB.addReg(DestReg, RegState::Define);
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if (ZeroReg)
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MIB.addReg(ZeroReg);
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if (SrcReg)
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MIB.addReg(SrcReg, getKillRegState(KillSrc));
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}
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static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
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unsigned Flag) {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned Align = MFI.getObjectAlignment(FI);
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return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
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MFI.getObjectSize(FI), Align);
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}
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void MipsInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
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unsigned Opc = 0;
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if (RC == Mips::CPURegsRegisterClass)
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Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
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else if (RC == Mips::CPU64RegsRegisterClass)
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Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
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else if (RC == Mips::FGR32RegisterClass)
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Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
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else if (RC == Mips::AFGR64RegisterClass)
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Opc = Mips::SDC1;
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else if (RC == Mips::FGR64RegisterClass)
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Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
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}
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void MipsInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
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unsigned Opc = 0;
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if (RC == Mips::CPURegsRegisterClass)
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Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
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else if (RC == Mips::CPU64RegsRegisterClass)
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Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
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else if (RC == Mips::FGR32RegisterClass)
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Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
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else if (RC == Mips::AFGR64RegisterClass)
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Opc = Mips::LDC1;
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else if (RC == Mips::FGR64RegisterClass)
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Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
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assert(Opc && "Register class not handled!");
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BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
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.addMemOperand(MMO);
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}
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MachineInstr*
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MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
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uint64_t Offset, const MDNode *MDPtr,
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DebugLoc DL) const {
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
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.addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
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return &*MIB;
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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static unsigned GetAnalyzableBrOpc(unsigned Opc) {
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return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
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Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
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Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
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Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
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Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
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Opc == Mips::J) ?
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Opc : 0;
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}
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
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{
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BEQ: return Mips::BNE;
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case Mips::BNE: return Mips::BEQ;
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case Mips::BGTZ: return Mips::BLEZ;
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case Mips::BGEZ: return Mips::BLTZ;
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case Mips::BLTZ: return Mips::BGEZ;
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case Mips::BLEZ: return Mips::BGTZ;
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case Mips::BEQ64: return Mips::BNE64;
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case Mips::BNE64: return Mips::BEQ64;
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case Mips::BGTZ64: return Mips::BLEZ64;
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case Mips::BGEZ64: return Mips::BLTZ64;
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case Mips::BLTZ64: return Mips::BGEZ64;
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case Mips::BLEZ64: return Mips::BGTZ64;
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case Mips::BC1T: return Mips::BC1F;
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case Mips::BC1F: return Mips::BC1T;
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}
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}
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static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand>& Cond) {
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assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
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int NumOp = Inst->getNumExplicitOperands();
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// for both int and fp branches, the last explicit operand is the
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// MBB.
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BB = Inst->getOperand(NumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(Opc));
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for (int i=0; i<NumOp-1; i++)
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Cond.push_back(Inst->getOperand(i));
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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if (I == REnd || !isUnpredicatedTerminator(&*I)) {
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// If this block ends with no branches (it just falls through to its succ)
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// just return false, leaving TBB/FBB null.
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TBB = FBB = NULL;
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return false;
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}
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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// Not an analyzable branch (must be an indirect jump).
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if (!GetAnalyzableBrOpc(LastOpc))
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return true;
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// Get the second to last instruction in the block.
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unsigned SecondLastOpc = 0;
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MachineInstr *SecondLastInst = NULL;
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if (++I != REnd) {
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SecondLastInst = &*I;
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SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
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// Not an analyzable branch (must be an indirect jump).
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if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
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return true;
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}
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// If there is only one terminator instruction, process it.
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if (!SecondLastOpc) {
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// Unconditional branch
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if (LastOpc == UncondBrOpc) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// Conditional branch
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AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
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return false;
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}
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// If we reached here, there are two branches.
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// If there are three terminators, we don't know what sort of block this is.
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if (++I != REnd && isUnpredicatedTerminator(&*I))
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return true;
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// If second to last instruction is an unconditional branch,
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// analyze it and remove the last instruction.
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if (SecondLastOpc == UncondBrOpc) {
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// Return if the last instruction cannot be removed.
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if (!AllowModify)
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return true;
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TBB = SecondLastInst->getOperand(0).getMBB();
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LastInst->eraseFromParent();
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return false;
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}
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// Conditional branch followed by an unconditional branch.
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// The last one must be unconditional.
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if (LastOpc != UncondBrOpc)
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return true;
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AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond)
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const {
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unsigned Opc = Cond[0].getImm();
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const MCInstrDesc &MCID = get(Opc);
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MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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for (unsigned i = 1; i < Cond.size(); ++i)
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MIB.addReg(Cond[i].getReg());
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MIB.addMBB(TBB);
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}
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unsigned MipsInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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// # of condition operands:
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// Unconditional branches: 0
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// Floating point branches: 1 (opc)
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// Int BranchZero: 2 (opc, reg)
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// Int Branch: 3 (opc, reg0, reg1)
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assert((Cond.size() <= 3) &&
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"# of Mips branch conditions must be <= 3!");
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// Two-way Conditional branch.
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if (FBB) {
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BuildCondBr(MBB, TBB, DL, Cond);
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BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
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return 2;
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}
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// One way branch.
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// Unconditional branch.
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if (Cond.empty())
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BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
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else // Conditional branch.
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BuildCondBr(MBB, TBB, DL, Cond);
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return 1;
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}
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unsigned MipsInstrInfo::
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RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
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MachineBasicBlock::reverse_iterator FirstBr;
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unsigned removed;
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// Skip all the debug instructions.
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while (I != REnd && I->isDebugValue())
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++I;
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FirstBr = I;
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// Up to 2 branches are removed.
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// Note that indirect branches are not removed.
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for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
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if (!GetAnalyzableBrOpc(I->getOpcode()))
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break;
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MBB.erase(I.base(), FirstBr.base());
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return removed;
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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/// specified Branch instruction.
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bool MipsInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
|
{
|
|
assert( (Cond.size() && Cond.size() <= 3) &&
|
|
"Invalid Mips branch condition!");
|
|
Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
|
|
return false;
|
|
}
|
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
/// the global base register value. Output instructions required to
|
|
/// initialize the register in the function entry block, if necessary.
|
|
///
|
|
unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
|
|
MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
|
|
unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
|
|
if (GlobalBaseReg != 0)
|
|
return GlobalBaseReg;
|
|
|
|
// Insert the set of GlobalBaseReg into the first MBB of the function
|
|
MachineBasicBlock &FirstMBB = MF->front();
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
|
|
unsigned GP = IsN64 ? Mips::GP_64 : Mips::GP;
|
|
const TargetRegisterClass *RC
|
|
= IsN64 ? Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
|
|
|
|
GlobalBaseReg = RegInfo.createVirtualRegister(RC);
|
|
BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
|
|
GlobalBaseReg).addReg(GP);
|
|
RegInfo.addLiveIn(GP);
|
|
|
|
MipsFI->setGlobalBaseReg(GlobalBaseReg);
|
|
return GlobalBaseReg;
|
|
}
|