llvm-6502/test/CodeGen
Renato Golin 4173058d07 [ARM] Add support for nest attribute using r12
Register r12 ('ip') is used by GCC for this purpose
and hence is used here. As discussed on the GCC mailing
list, the register choice is an ABI issue and so
choosing the same register as GCC means
__builtin_call_with_static_chain is compatible.

A similar patch has just gone in the AArch64 backend,
so this is just the ARM counterpart, following the same
discussion.

Patch by Stephen Cross.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241996 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-12 18:16:40 +00:00
..
AArch64 [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks. 2015-07-10 22:09:55 +00:00
AMDGPU DAGCombiner: Assume invariant load cannot alias a store 2015-07-10 22:17:40 +00:00
ARM [ARM] Add support for nest attribute using r12 2015-07-12 18:16:40 +00:00
BPF
CPP
Generic
Hexagon [Hexagon] Add support for atomic RMW operations 2015-07-09 14:51:21 +00:00
Inputs
Mips
MIR MIR Serialization: Serialize the virtual register operands. 2015-07-10 22:51:20 +00:00
MSP430
NVPTX Actually support volatile memcpys in NVPTX lowering 2015-07-10 15:40:33 +00:00
PowerPC [PowerPC] Make use of the TargetRecip system 2015-07-12 02:33:57 +00:00
SPARC [SPARC] Cleanup handling of the Y/ASR registers. 2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-10 18:28:49 +00:00
WebAssembly
WinEH [SEH] Push reloads of the SEH code past phi nodes 2015-07-10 22:21:54 +00:00
X86 [X86][SSE] Tidied up vector extend/truncation tests. NFCI. 2015-07-12 17:40:49 +00:00
XCore