mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
6c6344e6a9
pairwise implementation, using an overloaded definition instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196831 91177308-0d34-0410-b5e6-96231b3b80d8
246 lines
8.2 KiB
LLVM
246 lines
8.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64>)
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define <1 x i64> @test_addp_v1i64(<2 x i64> %a) {
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; CHECK: test_addp_v1i64:
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
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ret <1 x i64> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpfadd.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_faddp_v1f32(<2 x float> %a) {
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; CHECK: test_faddp_v1f32:
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; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpfadd.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpfadd.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_faddp_v1f64(<2 x double> %a) {
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; CHECK: test_faddp_v1f64:
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; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpfadd.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpmax.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fmaxp_v1f32(<2 x float> %a) {
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; CHECK: test_fmaxp_v1f32:
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; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpmax.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpmax.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fmaxp_v1f64(<2 x double> %a) {
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; CHECK: test_fmaxp_v1f64:
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; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpmax.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpmin.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fminp_v1f32(<2 x float> %a) {
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; CHECK: test_fminp_v1f32:
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; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpmin.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpmin.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fminp_v1f64(<2 x double> %a) {
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; CHECK: test_fminp_v1f64:
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; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpmin.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpfmaxnm.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fmaxnmp_v1f32(<2 x float> %a) {
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; CHECK: test_fmaxnmp_v1f32:
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; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpfmaxnm.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpfmaxnm.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fmaxnmp_v1f64(<2 x double> %a) {
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; CHECK: test_fmaxnmp_v1f64:
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; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpfmaxnm.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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declare <1 x float> @llvm.aarch64.neon.vpfminnm.v1f32.v2f32(<2 x float>)
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define <1 x float> @test_fminnmp_v1f32(<2 x float> %a) {
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; CHECK: test_fminnmp_v1f32:
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; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%val = call <1 x float> @llvm.aarch64.neon.vpfminnm.v1f32.v2f32(<2 x float> %a)
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ret <1 x float> %val
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}
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declare <1 x double> @llvm.aarch64.neon.vpfminnm.v1f64.v2f64(<2 x double>)
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define <1 x double> @test_fminnmp_v1f64(<2 x double> %a) {
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; CHECK: test_fminnmp_v1f64:
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; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%val = call <1 x double> @llvm.aarch64.neon.vpfminnm.v1f64.v2f64(<2 x double> %a)
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ret <1 x double> %val
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}
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define float @test_vaddv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vaddv_f32
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; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define float @test_vaddvq_f32(<4 x float> %a) {
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; CHECK-LABEL: test_vaddvq_f32
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; CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vaddvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vaddvq_f64
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; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vmaxv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vmaxv_f32
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; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vmaxvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vmaxvq_f64
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; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vminv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vminv_f32
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; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vminvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vminvq_f64
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; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define double @test_vmaxnmvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vmaxnmvq_f64
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; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vmaxnmv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vmaxnmv_f32
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; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define double @test_vminnmvq_f64(<2 x double> %a) {
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; CHECK-LABEL: test_vminnmvq_f64
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; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double> %a)
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%2 = extractelement <1 x double> %1, i32 0
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ret double %2
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}
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define float @test_vminnmv_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vminnmv_f32
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; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
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%1 = tail call <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float> %a)
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%2 = extractelement <1 x float> %1, i32 0
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ret float %2
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}
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define <2 x i64> @test_vpaddq_s64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpaddq_s64
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; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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%1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define <2 x i64> @test_vpaddq_u64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vpaddq_u64
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; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
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%1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define i64 @test_vaddvq_s64(<2 x i64> %a) {
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; CHECK-LABEL: test_vaddvq_s64
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
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%2 = extractelement <1 x i64> %1, i32 0
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ret i64 %2
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}
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define i64 @test_vaddvq_u64(<2 x i64> %a) {
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; CHECK-LABEL: test_vaddvq_u64
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; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
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%1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
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%2 = extractelement <1 x i64> %1, i32 0
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ret i64 %2
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}
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declare <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64>)
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declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
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declare <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double>)
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declare <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float>)
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declare <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double>)
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declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float>)
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declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float>) |