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https://github.com/c64scene-ar/llvm-6502.git
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fd0096a42c
ISD::VSELECT mask uses 1 to identify the first argument and 0 to identify the second argument. On the other hand, BLENDI uses 0 to identify the first argument and 1 to identify the second argument. Fix the generation of the blend mask to account for this difference. The bug did not show up with r209043, because we were not checking for the actual arguments of the blend instruction! This commit also fixes the test cases. Note: The same mask works for the BLENDr variant because the arguments are swapped during instruction selection (see the BLENDXXrr patterns). <rdar://problem/16975435> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209324 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.4 KiB
LLVM
41 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
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; Verify that we produce movss instead of blendvps when possible.
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;CHECK-LABEL: vsel_float:
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;CHECK-NOT: blend
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;CHECK: movss
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK-LABEL: vsel_4xi8:
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;CHECK-NOT: blend
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;CHECK: movss
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;CHECK: ret
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2
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ret <4 x i8> %vsel
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}
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;CHECK-LABEL: vsel_8xi16:
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; The select mask is
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; <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>
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; which translates into the boolean mask (big endian representation):
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; 00010001 = 17.
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; '1' means takes the first argument, '0' means takes the second argument.
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; This is the opposite of the intel syntax, thus we expect
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; the inverted mask: 11101110 = 238.
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; According to the ABI:
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; v1 is in xmm0 => first argument is xmm0.
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; v2 is in xmm1 => second argument is xmm1.
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;CHECK: pblendw $238, %xmm1, %xmm0
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;CHECK: ret
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define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2
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ret <8 x i16> %vsel
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}
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