mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6c76c959e4
This introduces a target specific streamer, X86WinCOFFStreamer, which handles the target specific behaviour (e.g. WinEH). This is mostly to ensure that differences between ARM and X86 remain disjoint and do not accidentally cross boundaries. This is the final staging change for enabling object emission for Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207344 91177308-0d34-0410-b5e6-96231b3b80d8
461 lines
15 KiB
C++
461 lines
15 KiB
C++
//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides X86 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "X86MCTargetDesc.h"
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#include "InstPrinter/X86ATTInstPrinter.h"
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#include "InstPrinter/X86IntelInstPrinter.h"
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#include "X86MCAsmInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/TargetRegistry.h"
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#if _MSC_VER
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#include <intrin.h>
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#endif
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using namespace llvm;
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#define GET_REGINFO_MC_DESC
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#include "X86GenRegisterInfo.inc"
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#define GET_INSTRINFO_MC_DESC
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#include "X86GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "X86GenSubtargetInfo.inc"
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std::string X86_MC::ParseX86Triple(StringRef TT) {
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Triple TheTriple(TT);
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std::string FS;
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if (TheTriple.getArch() == Triple::x86_64)
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FS = "+64bit-mode,-32bit-mode,-16bit-mode";
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else if (TheTriple.getEnvironment() != Triple::CODE16)
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FS = "-64bit-mode,+32bit-mode,-16bit-mode";
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else
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FS = "-64bit-mode,-32bit-mode,+16bit-mode";
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return FS;
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}
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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int registers[4];
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__cpuid(registers, value);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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}
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/// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
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/// 4 values in the specified arguments. If we can't run cpuid on the host,
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/// return true.
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bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
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#if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
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asm ("movq\t%%rbx, %%rsi\n\t"
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"cpuid\n\t"
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"xchgq\t%%rbx, %%rsi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value),
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"c" (subleaf));
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return false;
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#elif defined(_MSC_VER)
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// __cpuidex was added in MSVC++ 9.0 SP1
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#if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
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int registers[4];
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__cpuidex(registers, value, subleaf);
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*rEAX = registers[0];
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*rEBX = registers[1];
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*rECX = registers[2];
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*rEDX = registers[3];
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return false;
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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#elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
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#if defined(__GNUC__)
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asm ("movl\t%%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl\t%%ebx, %%esi\n\t"
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: "=a" (*rEAX),
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"=S" (*rEBX),
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"=c" (*rECX),
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"=d" (*rEDX)
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: "a" (value),
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"c" (subleaf));
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return false;
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#elif defined(_MSC_VER)
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__asm {
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mov eax,value
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mov ecx,subleaf
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cpuid
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mov esi,rEAX
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mov dword ptr [esi],eax
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mov esi,rEBX
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mov dword ptr [esi],ebx
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mov esi,rECX
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mov dword ptr [esi],ecx
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mov esi,rEDX
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mov dword ptr [esi],edx
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}
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return false;
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#else
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return true;
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#endif
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#else
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return true;
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#endif
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}
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void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
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unsigned &Model) {
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Family = (EAX >> 8) & 0xf; // Bits 8 - 11
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Model = (EAX >> 4) & 0xf; // Bits 4 - 7
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if (Family == 6 || Family == 0xf) {
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if (Family == 0xf)
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// Examine extended family ID if family ID is F.
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Family += (EAX >> 20) & 0xff; // Bits 20 - 27
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// Examine extended model ID if family ID is 6 or F.
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Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
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}
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}
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unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
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Triple TheTriple(TT);
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if (TheTriple.getArch() == Triple::x86_64)
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return DWARFFlavour::X86_64;
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if (TheTriple.isOSDarwin())
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return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
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if (TheTriple.isOSCygMing())
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// Unsupported by now, just quick fallback
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return DWARFFlavour::X86_32_Generic;
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return DWARFFlavour::X86_32_Generic;
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}
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void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
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// FIXME: TableGen these.
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for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
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unsigned SEH = MRI->getEncodingValue(Reg);
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MRI->mapLLVMRegToSEHReg(Reg, SEH);
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}
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}
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MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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std::string ArchFS = X86_MC::ParseX86Triple(TT);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "generic";
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
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return X;
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}
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static MCInstrInfo *createX86MCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitX86MCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
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Triple TheTriple(TT);
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unsigned RA = (TheTriple.getArch() == Triple::x86_64)
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? X86::RIP // Should have dwarf #16.
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: X86::EIP; // Should have dwarf #8.
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MCRegisterInfo *X = new MCRegisterInfo();
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InitX86MCRegisterInfo(X, RA,
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X86_MC::getDwarfRegFlavour(TT, false),
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X86_MC::getDwarfRegFlavour(TT, true),
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RA);
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X86_MC::InitLLVM2SEHRegisterMapping(X);
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return X;
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}
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static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
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Triple TheTriple(TT);
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bool is64Bit = TheTriple.getArch() == Triple::x86_64;
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MCAsmInfo *MAI;
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if (TheTriple.isOSBinFormatMachO()) {
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if (is64Bit)
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MAI = new X86_64MCAsmInfoDarwin(TheTriple);
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else
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MAI = new X86MCAsmInfoDarwin(TheTriple);
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} else if (TheTriple.isOSBinFormatELF()) {
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// Force the use of an ELF container.
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MAI = new X86ELFMCAsmInfo(TheTriple);
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} else if (TheTriple.isWindowsMSVCEnvironment()) {
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MAI = new X86MCAsmInfoMicrosoft(TheTriple);
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} else if (TheTriple.isOSCygMing()) {
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MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
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} else {
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// The default is ELF.
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MAI = new X86ELFMCAsmInfo(TheTriple);
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}
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// Initialize initial frame state.
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// Calculate amount of bytes used for return address storing
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int stackGrowth = is64Bit ? -8 : -4;
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// Initial state of the frame pointer is esp+stackGrowth.
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unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
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nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
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MAI->addInitialFrameState(Inst);
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// Add return address to move list
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unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
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MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
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nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
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MAI->addInitialFrameState(Inst2);
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return MAI;
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}
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static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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Triple T(TT);
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bool is64Bit = T.getArch() == Triple::x86_64;
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if (RM == Reloc::Default) {
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// Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
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// Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
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// use static relocation model by default.
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if (T.isOSDarwin()) {
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if (is64Bit)
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RM = Reloc::PIC_;
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else
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RM = Reloc::DynamicNoPIC;
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} else if (T.isOSWindows() && is64Bit)
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RM = Reloc::PIC_;
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else
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RM = Reloc::Static;
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}
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// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
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// is defined as a model for code which may be used in static or dynamic
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// executables but not necessarily a shared library. On X86-32 we just
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// compile in -static mode, in x86-64 we use PIC.
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if (RM == Reloc::DynamicNoPIC) {
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if (is64Bit)
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RM = Reloc::PIC_;
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else if (!T.isOSDarwin())
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RM = Reloc::Static;
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}
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// If we are on Darwin, disallow static relocation model in X86-64 mode, since
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// the Mach-O file format doesn't support it.
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if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
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RM = Reloc::PIC_;
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// For static codegen, if we're not already set, use Small codegen.
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if (CM == CodeModel::Default)
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CM = CodeModel::Small;
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else if (CM == CodeModel::JITDefault)
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// 64-bit JIT places everything in the same buffer except external funcs.
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CM = is64Bit ? CodeModel::Large : CodeModel::Small;
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &_OS,
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MCCodeEmitter *_Emitter,
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const MCSubtargetInfo &STI,
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bool RelaxAll,
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bool NoExecStack) {
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Triple TheTriple(TT);
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switch (TheTriple.getObjectFormat()) {
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default: llvm_unreachable("unsupported object format");
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case Triple::MachO:
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return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
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case Triple::COFF:
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assert(TheTriple.isOSWindows() && "only Windows COFF is supported");
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return createX86WinCOFFStreamer(Ctx, MAB, _Emitter, _OS, RelaxAll);
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case Triple::ELF:
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return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
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}
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}
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static MCInstPrinter *createX86MCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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if (SyntaxVariant == 0)
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return new X86ATTInstPrinter(MAI, MII, MRI);
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if (SyntaxVariant == 1)
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return new X86IntelInstPrinter(MAI, MII, MRI);
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return nullptr;
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}
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static MCRelocationInfo *createX86MCRelocationInfo(StringRef TT,
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MCContext &Ctx) {
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Triple TheTriple(TT);
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if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
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return createX86_64MachORelocationInfo(Ctx);
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else if (TheTriple.isOSBinFormatELF())
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return createX86_64ELFRelocationInfo(Ctx);
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// Default to the stock relocation info.
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return llvm::createMCRelocationInfo(TT, Ctx);
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}
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static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
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return new MCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeX86TargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
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RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
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// Register the MC codegen info.
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RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
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RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
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X86_MC::createX86MCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
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X86_MC::createX86MCSubtargetInfo);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
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createX86MCInstrAnalysis);
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TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
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createX86MCInstrAnalysis);
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// Register the code emitter.
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TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
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createX86MCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
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createX86MCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
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createX86_32AsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
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createX86_64AsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
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createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
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createMCStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
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createX86MCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
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createX86MCInstPrinter);
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// Register the MC relocation info.
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TargetRegistry::RegisterMCRelocationInfo(TheX86_32Target,
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createX86MCRelocationInfo);
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TargetRegistry::RegisterMCRelocationInfo(TheX86_64Target,
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createX86MCRelocationInfo);
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}
|