mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
31d157ae1a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
409 lines
16 KiB
TableGen
409 lines
16 KiB
TableGen
//====-- SPU64InstrInfo.td - Cell SPU 64-bit operations ---*- tablegen -*--===//
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//
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// Cell SPU 64-bit operations
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//
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//===----------------------------------------------------------------------===//
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// 64-bit comparisons:
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//
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// 1. The instruction sequences for vector vice scalar differ by a
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// constant. In the scalar case, we're only interested in the
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// top two 32-bit slots, whereas we're interested in an exact
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// all-four-slot match in the vector case.
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//
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// 2. There are no "immediate" forms, since loading 64-bit constants
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// could be a constant pool load.
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//
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// 3. i64 setcc results are i32, which are subsequently converted to a FSM
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// mask when used in a select pattern.
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//
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// 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
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// [Note: this may be moot, since gb produces v4i32 or r32.]
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//
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// 5. The code sequences for r64 and v2i64 are probably overly conservative,
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// compared to the code that gcc produces.
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//
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// M00$E B!tes Kan be Pretty N@sTi!!!!! (apologies to Monty!)
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// selb instruction definition for i64. Note that the selection mask is
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// a vector, produced by various forms of FSM:
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def SELBr64_cond:
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SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
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[/* no pattern */]>;
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// The generic i64 select pattern, which assumes that the comparison result
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// is in a 32-bit register that contains a select mask pattern (i.e., gather
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// bits result):
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def : Pat<(select R32C:$rCond, R64C:$rFalse, R64C:$rTrue),
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(SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 R32C:$rCond))>;
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// select the negative condition:
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class I64SELECTNegCond<PatFrag cond, CodeFrag compare>:
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Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
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(SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 compare.Fragment))>;
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// setcc the negative condition:
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class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
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Pat<(cond R64C:$rA, R64C:$rB),
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(XORIr32 compare.Fragment, -1)>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// The i64 seteq fragment that does the scalar->vector conversion and
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// comparison:
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def CEQr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG))), 0xb)>;
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// The i64 seteq fragment that does the vector comparison
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def CEQv2i64compare:
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CodeFrag<(CEQIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)), 0xf)>;
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// i64 seteq (equality): the setcc result is i32, which is converted to a
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// vector FSM mask when used in a select pattern.
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//
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// v2i64 seteq (equality): the setcc result is v4i32
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multiclass CompareEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQr64compare.Fragment, R32C))>;
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def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CEQr64compare.Fragment), R32C))>;
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def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CEQv2i64compare.Fragment), R32C))>;
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}
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defm I64EQ: CompareEqual64;
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def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
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def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
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// i64 setne:
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def : I64SETCCNegCond<setne, I64EQr64>;
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def : I64SELECTNegCond<setne, I64EQr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setugt/setule:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CLGTr64ugt:
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CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG))>;
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def CLGTr64eq:
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CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG))>;
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def CLGTr64compare:
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CodeFrag<(SELBv2i64 CLGTr64ugt.Fragment,
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(XSWDv2i64 CLGTr64ugt.Fragment),
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CLGTr64eq.Fragment)>;
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def CLGTv2i64ugt:
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CodeFrag<(CLGTv4i32 VECREG:$rA, VECREG:$rB)>;
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def CLGTv2i64eq:
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CodeFrag<(CEQv4i32 VECREG:$rA, VECREG:$rB)>;
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def CLGTv2i64compare:
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CodeFrag<(SELBv2i64 CLGTv2i64ugt.Fragment,
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(XSWDv2i64 CLGTr64ugt.Fragment),
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CLGTv2i64eq.Fragment)>;
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multiclass CompareLogicalGreaterThan64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CLGTr64compare.Fragment, R32C))>;
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def v2i64: CodeFrag<CLGTv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CLGTr64compare.Fragment), R32C))>;
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def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CLGTv2i64compare.Fragment), R32C))>;
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}
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defm I64LGT: CompareLogicalGreaterThan64;
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def : Pat<(setugt R64C:$rA, R64C:$rB), I64LGTr64.Fragment>;
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//def : Pat<(setugt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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// I64LGTv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setule, I64LGTr64>;
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def : I64SELECTNegCond<setule, I64LGTr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setuge/setult:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CLGEr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (ORv4i32 CLGTr64ugt.Fragment,
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CLGTr64eq.Fragment)), 0xb)>;
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def CLGEv2i64compare:
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CodeFrag<(CEQIv4i32 (GBv4i32 (ORv4i32 CLGTv2i64ugt.Fragment,
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CLGTv2i64eq.Fragment)), 0xf)>;
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multiclass CompareLogicalGreaterEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CLGEr64compare.Fragment, R32C))>;
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def v2i64: CodeFrag<CLGEv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CLGEr64compare.Fragment), R32C))>;
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def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CLGEv2i64compare.Fragment),R32C))>;
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}
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defm I64LGE: CompareLogicalGreaterEqual64;
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def : Pat<(setuge R64C:$rA, R64C:$rB), I64LGEr64.Fragment>;
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def : Pat<(v2i64 (setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))),
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I64LGEv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setult, I64LGEr64>;
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def : I64SELECTNegCond<setult, I64LGEr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setgt/setle:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CGTr64sgt:
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CodeFrag<(CGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG))>;
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def CGTr64eq:
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CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG))>;
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def CGTr64compare:
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CodeFrag<(SELBv2i64 CGTr64sgt.Fragment,
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(XSWDv2i64 CGTr64sgt.Fragment),
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CGTr64eq.Fragment)>;
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def CGTv2i64sgt:
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CodeFrag<(CGTv4i32 VECREG:$rA, VECREG:$rB)>;
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def CGTv2i64eq:
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CodeFrag<(CEQv4i32 VECREG:$rA, VECREG:$rB)>;
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def CGTv2i64compare:
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CodeFrag<(SELBv2i64 CGTv2i64sgt.Fragment,
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(XSWDv2i64 CGTr64sgt.Fragment),
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CGTv2i64eq.Fragment)>;
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multiclass CompareGreaterThan64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CGTr64compare.Fragment, R32C))>;
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def v2i64: CodeFrag<CGTv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CGTr64compare.Fragment), R32C))>;
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def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
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(FSMv4i32 CGTv2i64compare.Fragment), R32C))>;
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}
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defm I64GT: CompareLogicalGreaterThan64;
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def : Pat<(setgt R64C:$rA, R64C:$rB), I64GTr64.Fragment>;
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//def : Pat<(setgt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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// I64GTv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setle, I64GTr64>;
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def : I64SELECTNegCond<setle, I64GTr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// i64 setge/setlt:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def CGEr64compare:
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CodeFrag<(CGTIv4i32 (GBv4i32 (ORv4i32 CGTr64sgt.Fragment,
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CGTr64eq.Fragment)), 0xb)>;
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def CGEv2i64compare:
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CodeFrag<(CEQIv4i32 (GBv4i32 (ORv4i32 CGTv2i64sgt.Fragment,
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CGTv2i64eq.Fragment)), 0xf)>;
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multiclass CompareGreaterEqual64 {
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// Plain old comparison, converts back to i32 scalar
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def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CGEr64compare.Fragment, R32C))>;
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def v2i64: CodeFrag<CGEv2i64compare.Fragment>;
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// SELB mask from FSM:
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def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS (FSMv4i32 CGEr64compare.Fragment),R32C))>;
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def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS (FSMv4i32 CGEv2i64compare.Fragment),R32C))>;
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}
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defm I64GE: CompareGreaterEqual64;
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def : Pat<(setge R64C:$rA, R64C:$rB), I64GEr64.Fragment>;
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def : Pat<(v2i64 (setge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))),
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I64GEv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setlt, I64GEr64>;
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def : I64SELECTNegCond<setlt, I64GEr64>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// v2i64, i64 add
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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class v2i64_add_cg<dag lhs, dag rhs>:
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CodeFrag<(CGv4i32 lhs, rhs)>;
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class v2i64_add_1<dag lhs, dag rhs, dag cg, dag cg_mask>:
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CodeFrag<(ADDXv4i32 lhs, rhs, (SHUFBv4i32 cg, cg, cg_mask))>;
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class v2i64_add<dag lhs, dag rhs, dag cg_mask>:
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v2i64_add_1<lhs, rhs, v2i64_add_cg<lhs, rhs>.Fragment, cg_mask>;
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def : Pat<(SPUadd64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)),
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(COPY_TO_REGCLASS v2i64_add<(COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG),
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(v4i32 VECREG:$rCGmask)>.Fragment, R64C)>;
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def : Pat<(SPUadd64 (v2i64 VECREG:$rA), (v2i64 VECREG:$rB),
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(v4i32 VECREG:$rCGmask)),
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v2i64_add<(v2i64 VECREG:$rA),
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(v2i64 VECREG:$rB),
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(v4i32 VECREG:$rCGmask)>.Fragment>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// v2i64, i64 subtraction
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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class v2i64_sub_bg<dag lhs, dag rhs>: CodeFrag<(BGv4i32 lhs, rhs)>;
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class v2i64_sub<dag lhs, dag rhs, dag bg, dag bg_mask>:
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CodeFrag<(SFXv4i32 lhs, rhs, (SHUFBv4i32 bg, bg, bg_mask))>;
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def : Pat<(SPUsub64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)),
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(COPY_TO_REGCLASS
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v2i64_sub<(COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG),
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v2i64_sub_bg<(COPY_TO_REGCLASS R64C:$rA, VECREG),
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(COPY_TO_REGCLASS R64C:$rB, VECREG)>.Fragment,
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(v4i32 VECREG:$rCGmask)>.Fragment, R64C)>;
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def : Pat<(SPUsub64 (v2i64 VECREG:$rA), (v2i64 VECREG:$rB),
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(v4i32 VECREG:$rCGmask)),
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v2i64_sub<(v2i64 VECREG:$rA),
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(v2i64 VECREG:$rB),
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v2i64_sub_bg<(v2i64 VECREG:$rA),
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(v2i64 VECREG:$rB)>.Fragment,
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(v4i32 VECREG:$rCGmask)>.Fragment>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// v2i64, i64 multiply
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//
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// Note: i64 multiply is simply the vector->scalar conversion of the
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// full-on v2i64 multiply, since the entire vector has to be manipulated
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// anyway.
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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class v2i64_mul_ahi64<dag rA> :
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CodeFrag<(SELBv4i32 rA, (ILv4i32 0), (FSMBIv4i32 0x0f0f))>;
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class v2i64_mul_bhi64<dag rB> :
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CodeFrag<(SELBv4i32 rB, (ILv4i32 0), (FSMBIv4i32 0x0f0f))>;
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class v2i64_mul_alo64<dag rB> :
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CodeFrag<(SELBv4i32 rB, (ILv4i32 0), (FSMBIv4i32 0xf0f0))>;
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class v2i64_mul_blo64<dag rB> :
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CodeFrag<(SELBv4i32 rB, (ILv4i32 0), (FSMBIv4i32 0xf0f0))>;
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class v2i64_mul_ashlq2<dag rA>:
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CodeFrag<(SHLQBYIv4i32 rA, 0x2)>;
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class v2i64_mul_ashlq4<dag rA>:
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CodeFrag<(SHLQBYIv4i32 rA, 0x4)>;
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class v2i64_mul_bshlq2<dag rB> :
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CodeFrag<(SHLQBYIv4i32 rB, 0x2)>;
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class v2i64_mul_bshlq4<dag rB> :
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CodeFrag<(SHLQBYIv4i32 rB, 0x4)>;
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class v2i64_highprod<dag rA, dag rB>:
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CodeFrag<(Av4i32
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(Av4i32
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(MPYUv4i32 v2i64_mul_bshlq4<rB>.Fragment, // a1 x b3
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v2i64_mul_ahi64<rA>.Fragment),
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(MPYHv4i32 v2i64_mul_ahi64<rA>.Fragment, // a0 x b3
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v2i64_mul_bshlq4<rB>.Fragment)),
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(Av4i32
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(MPYHv4i32 v2i64_mul_bhi64<rB>.Fragment,
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v2i64_mul_ashlq4<rA>.Fragment),
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(Av4i32
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(MPYHv4i32 v2i64_mul_ashlq4<rA>.Fragment,
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v2i64_mul_bhi64<rB>.Fragment),
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(Av4i32
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(MPYUv4i32 v2i64_mul_ashlq4<rA>.Fragment,
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v2i64_mul_bhi64<rB>.Fragment),
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(Av4i32
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(MPYHv4i32 v2i64_mul_ashlq2<rA>.Fragment,
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v2i64_mul_bshlq2<rB>.Fragment),
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(MPYUv4i32 v2i64_mul_ashlq2<rA>.Fragment,
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v2i64_mul_bshlq2<rB>.Fragment))))))>;
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class v2i64_mul_a3_b3<dag rA, dag rB>:
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CodeFrag<(MPYUv4i32 v2i64_mul_alo64<rA>.Fragment,
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v2i64_mul_blo64<rB>.Fragment)>;
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class v2i64_mul_a2_b3<dag rA, dag rB>:
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CodeFrag<(SELBv4i32 (SHLQBYIv4i32
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(MPYHHUv4i32 v2i64_mul_alo64<rA>.Fragment,
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|
v2i64_mul_bshlq2<rB>.Fragment), 0x2),
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(ILv4i32 0),
|
|
(FSMBIv4i32 0xc3c3))>;
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|
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class v2i64_mul_a3_b2<dag rA, dag rB>:
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CodeFrag<(SELBv4i32 (SHLQBYIv4i32
|
|
(MPYHHUv4i32 v2i64_mul_blo64<rB>.Fragment,
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|
v2i64_mul_ashlq2<rA>.Fragment), 0x2),
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(ILv4i32 0),
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(FSMBIv4i32 0xc3c3))>;
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|
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class v2i64_lowsum<dag rA, dag rB, dag rCGmask>:
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v2i64_add<v2i64_add<v2i64_mul_a3_b3<rA, rB>.Fragment,
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v2i64_mul_a2_b3<rA, rB>.Fragment, rCGmask>.Fragment,
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v2i64_mul_a3_b2<rA, rB>.Fragment, rCGmask>;
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|
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class v2i64_mul<dag rA, dag rB, dag rCGmask>:
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v2i64_add<v2i64_lowsum<rA, rB, rCGmask>.Fragment,
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(SELBv4i32 v2i64_highprod<rA, rB>.Fragment,
|
|
(ILv4i32 0),
|
|
(FSMBIv4i32 0x0f0f)),
|
|
rCGmask>;
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|
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def : Pat<(SPUmul64 R64C:$rA, R64C:$rB, (v4i32 VECREG:$rCGmask)),
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(COPY_TO_REGCLASS v2i64_mul<(COPY_TO_REGCLASS R64C:$rA, VECREG),
|
|
(COPY_TO_REGCLASS R64C:$rB, VECREG),
|
|
(v4i32 VECREG:$rCGmask)>.Fragment, R64C)>;
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|
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def : Pat<(SPUmul64 (v2i64 VECREG:$rA), (v2i64 VECREG:$rB),
|
|
(v4i32 VECREG:$rCGmask)),
|
|
v2i64_mul<(v2i64 VECREG:$rA), (v2i64 VECREG:$rB),
|
|
(v4i32 VECREG:$rCGmask)>.Fragment>;
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|
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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|
// f64 comparisons
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|
//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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|
// selb instruction definition for i64. Note that the selection mask is
|
|
// a vector, produced by various forms of FSM:
|
|
def SELBf64_cond:
|
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SELBInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB, R32C:$rC),
|
|
[(set R64FP:$rT,
|
|
(select R32C:$rC, R64FP:$rB, R64FP:$rA))]>;
|