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classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231954 91177308-0d34-0410-b5e6-96231b3b80d8
481 lines
13 KiB
C++
481 lines
13 KiB
C++
//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Insert wait instructions for memory reads and writes.
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///
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/// Memory reads and writes are issued asynchronously, so we need to insert
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/// S_WAITCNT instructions when we want to access any of their results or
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/// overwrite any register that's used asynchronously.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace {
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/// \brief One variable for each of the hardware counters
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typedef union {
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struct {
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unsigned VM;
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unsigned EXP;
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unsigned LGKM;
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} Named;
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unsigned Array[3];
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} Counters;
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typedef enum {
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OTHER,
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SMEM,
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VMEM
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} InstType;
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typedef Counters RegCounters[512];
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typedef std::pair<unsigned, unsigned> RegInterval;
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class SIInsertWaits : public MachineFunctionPass {
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private:
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static char ID;
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const SIInstrInfo *TII;
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const SIRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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/// \brief Constant hardware limits
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static const Counters WaitCounts;
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/// \brief Constant zero value
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static const Counters ZeroCounts;
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/// \brief Counter values we have already waited on.
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Counters WaitedOn;
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/// \brief Counter values for last instruction issued.
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Counters LastIssued;
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/// \brief Registers used by async instructions.
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RegCounters UsedRegs;
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/// \brief Registers defined by async instructions.
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RegCounters DefinedRegs;
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/// \brief Different export instruction types seen since last wait.
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unsigned ExpInstrTypesSeen;
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/// \brief Type of the last opcode.
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InstType LastOpcodeType;
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bool LastInstWritesM0;
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/// \brief Get increment/decrement amount for this instruction.
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Counters getHwCounts(MachineInstr &MI);
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/// \brief Is operand relevant for async execution?
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bool isOpRelevant(MachineOperand &Op);
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/// \brief Get register interval an operand affects.
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RegInterval getRegInterval(MachineOperand &Op);
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/// \brief Handle instructions async components
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void pushInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I);
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/// \brief Insert the actual wait instruction
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bool insertWait(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const Counters &Counts);
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/// \brief Do we need def2def checks?
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bool unorderedDefines(MachineInstr &MI);
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/// \brief Resolve all operand dependencies to counter requirements
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Counters handleOperands(MachineInstr &MI);
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/// \brief Insert S_NOP between an instruction writing M0 and S_SENDMSG.
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void handleSendMsg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
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public:
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SIInsertWaits(TargetMachine &tm) :
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MachineFunctionPass(ID),
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TII(nullptr),
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TRI(nullptr),
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ExpInstrTypesSeen(0) { }
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI insert wait instructions";
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}
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};
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} // End anonymous namespace
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char SIInsertWaits::ID = 0;
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const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
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const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };
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FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) {
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return new SIInsertWaits(tm);
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}
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Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
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uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags;
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Counters Result;
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Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
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// Only consider stores or EXP for EXP_CNT
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Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
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(MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore()));
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// LGKM may uses larger values
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if (TSFlags & SIInstrFlags::LGKM_CNT) {
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if (TII->isSMRD(MI.getOpcode())) {
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MachineOperand &Op = MI.getOperand(0);
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assert(Op.isReg() && "First LGKM operand must be a register!");
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unsigned Reg = Op.getReg();
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unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
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Result.Named.LGKM = Size > 4 ? 2 : 1;
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} else {
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// DS
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Result.Named.LGKM = 1;
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}
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} else {
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Result.Named.LGKM = 0;
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}
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return Result;
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}
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bool SIInsertWaits::isOpRelevant(MachineOperand &Op) {
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// Constants are always irrelevant
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if (!Op.isReg())
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return false;
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// Defines are always relevant
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if (Op.isDef())
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return true;
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// For exports all registers are relevant
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MachineInstr &MI = *Op.getParent();
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if (MI.getOpcode() == AMDGPU::EXP)
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return true;
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// For stores the stored value is also relevant
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if (!MI.getDesc().mayStore())
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return false;
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// Check if this operand is the value being stored.
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// Special case for DS instructions, since the address
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// operand comes before the value operand and it may have
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// multiple data operands.
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if (TII->isDS(MI.getOpcode())) {
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MachineOperand *Data = TII->getNamedOperand(MI, AMDGPU::OpName::data);
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if (Data && Op.isIdenticalTo(*Data))
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return true;
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MachineOperand *Data0 = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
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if (Data0 && Op.isIdenticalTo(*Data0))
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return true;
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MachineOperand *Data1 = TII->getNamedOperand(MI, AMDGPU::OpName::data1);
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if (Data1 && Op.isIdenticalTo(*Data1))
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return true;
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return false;
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}
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// NOTE: This assumes that the value operand is before the
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// address operand, and that there is only one value operand.
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for (MachineInstr::mop_iterator I = MI.operands_begin(),
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E = MI.operands_end(); I != E; ++I) {
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if (I->isReg() && I->isUse())
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return Op.isIdenticalTo(*I);
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}
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return false;
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}
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RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
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if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()))
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return std::make_pair(0, 0);
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unsigned Reg = Op.getReg();
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unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
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assert(Size >= 4);
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RegInterval Result;
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Result.first = TRI->getEncodingValue(Reg);
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Result.second = Result.first + Size / 4;
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return Result;
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}
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void SIInsertWaits::pushInstruction(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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// Get the hardware counter increments and sum them up
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Counters Increment = getHwCounts(*I);
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unsigned Sum = 0;
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for (unsigned i = 0; i < 3; ++i) {
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LastIssued.Array[i] += Increment.Array[i];
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Sum += Increment.Array[i];
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}
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// If we don't increase anything then that's it
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if (Sum == 0) {
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LastOpcodeType = OTHER;
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return;
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}
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if (MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
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AMDGPUSubtarget::VOLCANIC_ISLANDS) {
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// Any occurence of consecutive VMEM or SMEM instructions forms a VMEM
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// or SMEM clause, respectively.
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//
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// The temporary workaround is to break the clauses with S_NOP.
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//
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// The proper solution would be to allocate registers such that all source
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// and destination registers don't overlap, e.g. this is illegal:
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// r0 = load r2
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// r2 = load r0
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if ((LastOpcodeType == SMEM && TII->isSMRD(I->getOpcode())) ||
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(LastOpcodeType == VMEM && Increment.Named.VM)) {
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// Insert a NOP to break the clause.
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BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP))
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.addImm(0);
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LastInstWritesM0 = false;
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}
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if (TII->isSMRD(I->getOpcode()))
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LastOpcodeType = SMEM;
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else if (Increment.Named.VM)
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LastOpcodeType = VMEM;
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}
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// Remember which export instructions we have seen
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if (Increment.Named.EXP) {
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ExpInstrTypesSeen |= I->getOpcode() == AMDGPU::EXP ? 1 : 2;
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}
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for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
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MachineOperand &Op = I->getOperand(i);
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if (!isOpRelevant(Op))
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continue;
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RegInterval Interval = getRegInterval(Op);
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for (unsigned j = Interval.first; j < Interval.second; ++j) {
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// Remember which registers we define
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if (Op.isDef())
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DefinedRegs[j] = LastIssued;
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// and which one we are using
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if (Op.isUse())
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UsedRegs[j] = LastIssued;
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}
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}
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}
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bool SIInsertWaits::insertWait(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const Counters &Required) {
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// End of program? No need to wait on anything
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if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM)
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return false;
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// Figure out if the async instructions execute in order
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bool Ordered[3];
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// VM_CNT is always ordered
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Ordered[0] = true;
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// EXP_CNT is unordered if we have both EXP & VM-writes
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Ordered[1] = ExpInstrTypesSeen == 3;
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// LGKM_CNT is handled as always unordered. TODO: Handle LDS and GDS
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Ordered[2] = false;
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// The values we are going to put into the S_WAITCNT instruction
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Counters Counts = WaitCounts;
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// Do we really need to wait?
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bool NeedWait = false;
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for (unsigned i = 0; i < 3; ++i) {
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if (Required.Array[i] <= WaitedOn.Array[i])
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continue;
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NeedWait = true;
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if (Ordered[i]) {
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unsigned Value = LastIssued.Array[i] - Required.Array[i];
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// Adjust the value to the real hardware possibilities.
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Counts.Array[i] = std::min(Value, WaitCounts.Array[i]);
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} else
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Counts.Array[i] = 0;
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// Remember on what we have waited on.
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WaitedOn.Array[i] = LastIssued.Array[i] - Counts.Array[i];
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}
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if (!NeedWait)
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return false;
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// Reset EXP_CNT instruction types
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if (Counts.Named.EXP == 0)
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ExpInstrTypesSeen = 0;
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// Build the wait instruction
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BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
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.addImm((Counts.Named.VM & 0xF) |
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((Counts.Named.EXP & 0x7) << 4) |
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((Counts.Named.LGKM & 0x7) << 8));
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LastOpcodeType = OTHER;
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LastInstWritesM0 = false;
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return true;
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}
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/// \brief helper function for handleOperands
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static void increaseCounters(Counters &Dst, const Counters &Src) {
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for (unsigned i = 0; i < 3; ++i)
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Dst.Array[i] = std::max(Dst.Array[i], Src.Array[i]);
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}
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Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
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Counters Result = ZeroCounts;
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// S_SENDMSG implicitly waits for all outstanding LGKM transfers to finish,
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// but we also want to wait for any other outstanding transfers before
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// signalling other hardware blocks
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if (MI.getOpcode() == AMDGPU::S_SENDMSG)
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return LastIssued;
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// For each register affected by this
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// instruction increase the result sequence
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &Op = MI.getOperand(i);
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RegInterval Interval = getRegInterval(Op);
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for (unsigned j = Interval.first; j < Interval.second; ++j) {
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if (Op.isDef()) {
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increaseCounters(Result, UsedRegs[j]);
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increaseCounters(Result, DefinedRegs[j]);
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}
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if (Op.isUse())
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increaseCounters(Result, DefinedRegs[j]);
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}
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}
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return Result;
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}
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void SIInsertWaits::handleSendMsg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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if (MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() <
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AMDGPUSubtarget::VOLCANIC_ISLANDS)
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return;
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// There must be "S_NOP 0" between an instruction writing M0 and S_SENDMSG.
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if (LastInstWritesM0 && I->getOpcode() == AMDGPU::S_SENDMSG) {
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BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_NOP)).addImm(0);
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LastInstWritesM0 = false;
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return;
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}
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// Set whether this instruction sets M0
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LastInstWritesM0 = false;
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unsigned NumOperands = I->getNumOperands();
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for (unsigned i = 0; i < NumOperands; i++) {
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const MachineOperand &Op = I->getOperand(i);
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if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0)
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LastInstWritesM0 = true;
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}
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}
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// FIXME: Insert waits listed in Table 4.2 "Required User-Inserted Wait States"
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// around other non-memory instructions.
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bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
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bool Changes = false;
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TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
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TRI =
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static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
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MRI = &MF.getRegInfo();
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WaitedOn = ZeroCounts;
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LastIssued = ZeroCounts;
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LastOpcodeType = OTHER;
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LastInstWritesM0 = false;
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memset(&UsedRegs, 0, sizeof(UsedRegs));
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memset(&DefinedRegs, 0, sizeof(DefinedRegs));
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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// Wait for everything before a barrier.
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if (I->getOpcode() == AMDGPU::S_BARRIER)
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Changes |= insertWait(MBB, I, LastIssued);
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else
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Changes |= insertWait(MBB, I, handleOperands(*I));
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pushInstruction(MBB, I);
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handleSendMsg(MBB, I);
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}
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// Wait for everything at the end of the MBB
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Changes |= insertWait(MBB, MBB.getFirstTerminator(), LastIssued);
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}
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return Changes;
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}
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