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https://github.com/c64scene-ar/llvm-6502.git
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74feef261a
shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
1.4 KiB
LLVM
74 lines
1.4 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 > %t
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; RUN: grep rol %t | count 3
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; RUN: grep ror %t | count 1
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; RUN: grep shld %t | count 2
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; RUN: grep shrd %t | count 2
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define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = shl i16 %x, %z
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%1 = sub i16 16, %z
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%2 = lshr i16 %x, %1
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%3 = or i16 %2, %0
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ret i16 %3
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}
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define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = shl i16 %y, %z
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%1 = sub i16 16, %z
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%2 = lshr i16 %x, %1
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%3 = or i16 %2, %0
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ret i16 %3
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}
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define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = lshr i16 %x, %z
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%1 = sub i16 16, %z
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%2 = shl i16 %x, %1
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%3 = or i16 %2, %0
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ret i16 %3
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}
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define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = lshr i16 %y, %z
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%1 = sub i16 16, %z
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%2 = shl i16 %x, %1
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%3 = or i16 %2, %0
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ret i16 %3
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}
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define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = lshr i16 %x, 11
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%1 = shl i16 %x, 5
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%2 = or i16 %0, %1
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ret i16 %2
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}
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define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = shl i16 %y, 5
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%1 = lshr i16 %x, 11
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%2 = or i16 %0, %1
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ret i16 %2
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}
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define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = lshr i16 %x, 5
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%1 = shl i16 %x, 11
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%2 = or i16 %0, %1
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ret i16 %2
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}
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define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone {
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entry:
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%0 = lshr i16 %y, 5
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%1 = shl i16 %x, 11
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%2 = or i16 %0, %1
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ret i16 %2
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}
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