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https://github.com/c64scene-ar/llvm-6502.git
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6d1e29d2f2
scheduling opportunities (extra instruction can go in between MOVT / MOVW pair removing the stall). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112546 91177308-0d34-0410-b5e6-96231b3b80d8
360 lines
14 KiB
C++
360 lines
14 KiB
C++
//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expand pseudo instructions into target
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// instructions to allow proper scheduling, if-conversion, and other late
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// optimizations. This pass should be run after register allocation but before
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// post- regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-pseudo"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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namespace {
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class ARMExpandPseudo : public MachineFunctionPass {
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// Constants for register spacing in NEON load/store instructions.
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enum NEONRegSpacing {
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SingleSpc,
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EvenDblSpc,
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OddDblSpc
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};
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public:
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static char ID;
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ARMExpandPseudo() : MachineFunctionPass(ID) {}
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM pseudo instruction expansion pass";
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}
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private:
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void TransferImpOps(MachineInstr &OldMI,
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MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
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bool ExpandMBB(MachineBasicBlock &MBB);
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void ExpandVST(MachineBasicBlock::iterator &MBBI, unsigned Opc,
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bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs);
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};
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char ARMExpandPseudo::ID = 0;
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}
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/// TransferImpOps - Transfer implicit operands on the pseudo instruction to
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/// the instructions created from the expansion.
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void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
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MachineInstrBuilder &UseMI,
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MachineInstrBuilder &DefMI) {
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const TargetInstrDesc &Desc = OldMI.getDesc();
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for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
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i != e; ++i) {
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const MachineOperand &MO = OldMI.getOperand(i);
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assert(MO.isReg() && MO.getReg());
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if (MO.isUse())
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UseMI.addReg(MO.getReg(), getKillRegState(MO.isKill()));
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else
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DefMI.addReg(MO.getReg(),
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getDefRegState(true) | getDeadRegState(MO.isDead()));
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}
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}
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/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
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/// operands to real VST instructions with D register operands.
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void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI,
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unsigned Opc, bool hasWriteBack,
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NEONRegSpacing RegSpc, unsigned NumRegs) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
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unsigned OpIdx = 0;
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if (hasWriteBack) {
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bool DstIsDead = MI.getOperand(OpIdx).isDead();
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unsigned DstReg = MI.getOperand(OpIdx++).getReg();
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MIB.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead));
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}
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// Copy the addrmode6 operands.
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bool AddrIsKill = MI.getOperand(OpIdx).isKill();
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MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill));
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MIB.addImm(MI.getOperand(OpIdx++).getImm());
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if (hasWriteBack) {
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// Copy the am6offset operand.
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bool OffsetIsKill = MI.getOperand(OpIdx).isKill();
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MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(OffsetIsKill));
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}
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bool SrcIsKill = MI.getOperand(OpIdx).isKill();
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unsigned SrcReg = MI.getOperand(OpIdx).getReg();
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unsigned D0, D1, D2, D3;
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if (RegSpc == SingleSpc) {
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D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
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D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
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D2 = TRI->getSubReg(SrcReg, ARM::dsub_2);
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D3 = TRI->getSubReg(SrcReg, ARM::dsub_3);
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} else if (RegSpc == EvenDblSpc) {
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D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
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D1 = TRI->getSubReg(SrcReg, ARM::dsub_2);
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D2 = TRI->getSubReg(SrcReg, ARM::dsub_4);
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D3 = TRI->getSubReg(SrcReg, ARM::dsub_6);
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} else {
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assert(RegSpc == OddDblSpc && "unknown register spacing for VST");
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D0 = TRI->getSubReg(SrcReg, ARM::dsub_1);
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D1 = TRI->getSubReg(SrcReg, ARM::dsub_3);
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D2 = TRI->getSubReg(SrcReg, ARM::dsub_5);
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D3 = TRI->getSubReg(SrcReg, ARM::dsub_7);
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}
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MIB.addReg(D0).addReg(D1);
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if (NumRegs > 2)
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MIB.addReg(D2);
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if (NumRegs > 3)
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MIB.addReg(D3);
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MIB = AddDefaultPred(MIB);
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TransferImpOps(MI, MIB, MIB);
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if (SrcIsKill)
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// Add an implicit kill for the super-reg.
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(*MIB).addRegisterKilled(SrcReg, TRI, true);
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MI.eraseFromParent();
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}
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bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock::iterator NMBBI = llvm::next(MBBI);
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bool ModifiedOp = true;
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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default:
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ModifiedOp = false;
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break;
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case ARM::tLDRpci_pic:
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case ARM::t2LDRpci_pic: {
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unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
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? ARM::tLDRpci : ARM::t2LDRpci;
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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MachineInstrBuilder MIB1 =
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(NewLdOpc), DstReg)
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.addOperand(MI.getOperand(1)));
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(*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::tPICADD))
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.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
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.addReg(DstReg)
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.addOperand(MI.getOperand(2));
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TransferImpOps(MI, MIB1, MIB2);
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MI.eraseFromParent();
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break;
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}
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case ARM::MOVi32imm:
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case ARM::t2MOVi32imm: {
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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const MachineOperand &MO = MI.getOperand(1);
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MachineInstrBuilder LO16, HI16;
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LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(Opcode == ARM::MOVi32imm ?
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ARM::MOVi16 : ARM::t2MOVi16),
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DstReg);
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HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(Opcode == ARM::MOVi32imm ?
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ARM::MOVTi16 : ARM::t2MOVTi16))
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.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
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.addReg(DstReg);
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if (MO.isImm()) {
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unsigned Imm = MO.getImm();
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unsigned Lo16 = Imm & 0xffff;
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unsigned Hi16 = (Imm >> 16) & 0xffff;
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LO16 = LO16.addImm(Lo16);
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HI16 = HI16.addImm(Hi16);
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} else {
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const GlobalValue *GV = MO.getGlobal();
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unsigned TF = MO.getTargetFlags();
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LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
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HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
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}
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(*LO16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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(*HI16).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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LO16.addImm(Pred).addReg(PredReg);
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HI16.addImm(Pred).addReg(PredReg);
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TransferImpOps(MI, LO16, HI16);
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MI.eraseFromParent();
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break;
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}
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case ARM::VMOVQQ: {
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unsigned DstReg = MI.getOperand(0).getReg();
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bool DstIsDead = MI.getOperand(0).isDead();
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unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
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unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
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unsigned SrcReg = MI.getOperand(1).getReg();
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bool SrcIsKill = MI.getOperand(1).isKill();
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unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
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unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
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MachineInstrBuilder Even =
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::VMOVQ))
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.addReg(EvenDst,
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getDefRegState(true) | getDeadRegState(DstIsDead))
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.addReg(EvenSrc, getKillRegState(SrcIsKill)));
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MachineInstrBuilder Odd =
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::VMOVQ))
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.addReg(OddDst,
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getDefRegState(true) | getDeadRegState(DstIsDead))
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.addReg(OddSrc, getKillRegState(SrcIsKill)));
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TransferImpOps(MI, Even, Odd);
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MI.eraseFromParent();
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}
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case ARM::VST1q8Pseudo:
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ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break;
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case ARM::VST1q16Pseudo:
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ExpandVST(MBBI, ARM::VST1q16, false, SingleSpc, 2); break;
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case ARM::VST1q32Pseudo:
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ExpandVST(MBBI, ARM::VST1q32, false, SingleSpc, 2); break;
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case ARM::VST1q64Pseudo:
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ExpandVST(MBBI, ARM::VST1q64, false, SingleSpc, 2); break;
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case ARM::VST1q8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q8_UPD, true, SingleSpc, 2); break;
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case ARM::VST1q16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q16_UPD, true, SingleSpc, 2); break;
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case ARM::VST1q32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q32_UPD, true, SingleSpc, 2); break;
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case ARM::VST1q64Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST1q64_UPD, true, SingleSpc, 2); break;
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case ARM::VST2d8Pseudo:
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ExpandVST(MBBI, ARM::VST2d8, false, SingleSpc, 2); break;
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case ARM::VST2d16Pseudo:
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ExpandVST(MBBI, ARM::VST2d16, false, SingleSpc, 2); break;
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case ARM::VST2d32Pseudo:
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ExpandVST(MBBI, ARM::VST2d32, false, SingleSpc, 2); break;
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case ARM::VST2q8Pseudo:
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ExpandVST(MBBI, ARM::VST2q8, false, SingleSpc, 4); break;
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case ARM::VST2q16Pseudo:
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ExpandVST(MBBI, ARM::VST2q16, false, SingleSpc, 4); break;
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case ARM::VST2q32Pseudo:
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ExpandVST(MBBI, ARM::VST2q32, false, SingleSpc, 4); break;
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case ARM::VST2d8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2d8_UPD, true, SingleSpc, 2); break;
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case ARM::VST2d16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2d16_UPD, true, SingleSpc, 2); break;
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case ARM::VST2d32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2d32_UPD, true, SingleSpc, 2); break;
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case ARM::VST2q8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2q8_UPD, true, SingleSpc, 4); break;
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case ARM::VST2q16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2q16_UPD, true, SingleSpc, 4); break;
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case ARM::VST2q32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST2q32_UPD, true, SingleSpc, 4); break;
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case ARM::VST3d8Pseudo:
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ExpandVST(MBBI, ARM::VST3d8, false, SingleSpc, 3); break;
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case ARM::VST3d16Pseudo:
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ExpandVST(MBBI, ARM::VST3d16, false, SingleSpc, 3); break;
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case ARM::VST3d32Pseudo:
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ExpandVST(MBBI, ARM::VST3d32, false, SingleSpc, 3); break;
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case ARM::VST1d64TPseudo:
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ExpandVST(MBBI, ARM::VST1d64T, false, SingleSpc, 3); break;
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case ARM::VST3d8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST3d8_UPD, true, SingleSpc, 3); break;
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case ARM::VST3d16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST3d16_UPD, true, SingleSpc, 3); break;
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case ARM::VST3d32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST3d32_UPD, true, SingleSpc, 3); break;
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case ARM::VST1d64TPseudo_UPD:
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ExpandVST(MBBI, ARM::VST1d64T_UPD, true, SingleSpc, 3); break;
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case ARM::VST3q8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST3q8_UPD, true, EvenDblSpc, 3); break;
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case ARM::VST3q16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST3q16_UPD, true, EvenDblSpc, 3); break;
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case ARM::VST3q32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST3q32_UPD, true, EvenDblSpc, 3); break;
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case ARM::VST3q8oddPseudo_UPD:
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ExpandVST(MBBI, ARM::VST3q8_UPD, true, OddDblSpc, 3); break;
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case ARM::VST3q16oddPseudo_UPD:
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ExpandVST(MBBI, ARM::VST3q16_UPD, true, OddDblSpc, 3); break;
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case ARM::VST3q32oddPseudo_UPD:
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ExpandVST(MBBI, ARM::VST3q32_UPD, true, OddDblSpc, 3); break;
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case ARM::VST4d8Pseudo:
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ExpandVST(MBBI, ARM::VST4d8, false, SingleSpc, 4); break;
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case ARM::VST4d16Pseudo:
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ExpandVST(MBBI, ARM::VST4d16, false, SingleSpc, 4); break;
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case ARM::VST4d32Pseudo:
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ExpandVST(MBBI, ARM::VST4d32, false, SingleSpc, 4); break;
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case ARM::VST1d64QPseudo:
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ExpandVST(MBBI, ARM::VST1d64Q, false, SingleSpc, 4); break;
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case ARM::VST4d8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST4d8_UPD, true, SingleSpc, 4); break;
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case ARM::VST4d16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST4d16_UPD, true, SingleSpc, 4); break;
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case ARM::VST4d32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST4d32_UPD, true, SingleSpc, 4); break;
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case ARM::VST1d64QPseudo_UPD:
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ExpandVST(MBBI, ARM::VST1d64Q_UPD, true, SingleSpc, 4); break;
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case ARM::VST4q8Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST4q8_UPD, true, EvenDblSpc, 4); break;
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case ARM::VST4q16Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST4q16_UPD, true, EvenDblSpc, 4); break;
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case ARM::VST4q32Pseudo_UPD:
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ExpandVST(MBBI, ARM::VST4q32_UPD, true, EvenDblSpc, 4); break;
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case ARM::VST4q8oddPseudo_UPD:
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ExpandVST(MBBI, ARM::VST4q8_UPD, true, OddDblSpc, 4); break;
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case ARM::VST4q16oddPseudo_UPD:
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ExpandVST(MBBI, ARM::VST4q16_UPD, true, OddDblSpc, 4); break;
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case ARM::VST4q32oddPseudo_UPD:
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ExpandVST(MBBI, ARM::VST4q32_UPD, true, OddDblSpc, 4); break;
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}
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if (ModifiedOp)
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Modified = true;
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getTarget().getInstrInfo();
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TRI = MF.getTarget().getRegisterInfo();
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bool Modified = false;
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for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
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++MFI)
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Modified |= ExpandMBB(*MFI);
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return Modified;
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}
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/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
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/// expansion pass.
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FunctionPass *llvm::createARMExpandPseudoPass() {
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return new ARMExpandPseudo();
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}
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