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42d9ca6299
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
541 lines
17 KiB
TableGen
541 lines
17 KiB
TableGen
//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MIPS register file
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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def sub_32 : SubRegIndex<32>;
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def sub_64 : SubRegIndex<64>;
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def sub_lo : SubRegIndex<32>;
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def sub_hi : SubRegIndex<32, 32>;
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def sub_dsp16_19 : SubRegIndex<4, 16>;
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def sub_dsp20 : SubRegIndex<1, 20>;
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def sub_dsp21 : SubRegIndex<1, 21>;
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def sub_dsp22 : SubRegIndex<1, 22>;
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def sub_dsp23 : SubRegIndex<1, 23>;
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}
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class Unallocatable {
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bit isAllocatable = 0;
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}
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// We have banks of 32 registers each.
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class MipsReg<bits<16> Enc, string n> : Register<n> {
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let HWEncoding = Enc;
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let Namespace = "Mips";
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}
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class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let HWEncoding = Enc;
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let Namespace = "Mips";
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}
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// Mips CPU Registers
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class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
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// Mips 64-bit CPU Registers
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class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_32];
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}
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// Mips 32-bit FPU Registers
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class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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// Mips 64-bit (aliased) FPU Registers
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class AFPR<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_lo, sub_hi];
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let CoveredBySubRegs = 1;
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}
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class AFPR64<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_lo, sub_hi];
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let CoveredBySubRegs = 1;
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}
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// Mips 128-bit (aliased) MSA Registers
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class AFPR128<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_64];
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}
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// Accumulator Registers
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class ACCReg<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_lo, sub_hi];
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let CoveredBySubRegs = 1;
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}
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// Mips Hardware Registers
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class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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// General Purpose Registers
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def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
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def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
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def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
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def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
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def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
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def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
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def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
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def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
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def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
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def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
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def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
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def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
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def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
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def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
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def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
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def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
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def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
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def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
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def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
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def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
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def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
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def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
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def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
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def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
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def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
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def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
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def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
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def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
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def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
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def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
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def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
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// General Purpose 64-bit Registers
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def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
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def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
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def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
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def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
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def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
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def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
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def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
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def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
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def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
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def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
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def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
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def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
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def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
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def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
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def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
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def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
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def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
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def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
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def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
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def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
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def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
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def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
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def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
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def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
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def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
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def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
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def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
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def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
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def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
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def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
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def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
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def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
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/// Mips Single point precision FPU Registers
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foreach I = 0-31 in
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def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
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// Higher half of 64-bit FP registers.
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foreach I = 0-31 in
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def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
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/// Mips Double point precision FPU Registers (aliased
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/// with the single precision to hold 64 bit values)
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foreach I = 0-15 in
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def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),
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[!cast<FPR>("F"#!shl(I, 1)),
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!cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
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/// Mips Double point precision FPU Registers in MFP64 mode.
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foreach I = 0-31 in
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def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
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DwarfRegNum<[!add(I, 32)]>;
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/// Mips MSA registers
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/// MSA and FPU cannot both be present unless the FPU has 64-bit registers
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foreach I = 0-31 in
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def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
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DwarfRegNum<[!add(I, 32)]>;
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// Hi/Lo registers
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def HI0 : Register<"ac0">, DwarfRegNum<[64]>;
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def HI1 : Register<"ac1">, DwarfRegNum<[176]>;
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def HI2 : Register<"ac2">, DwarfRegNum<[178]>;
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def HI3 : Register<"ac3">, DwarfRegNum<[180]>;
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def LO0 : Register<"ac0">, DwarfRegNum<[65]>;
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def LO1 : Register<"ac1">, DwarfRegNum<[177]>;
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def LO2 : Register<"ac2">, DwarfRegNum<[179]>;
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def LO3 : Register<"ac3">, DwarfRegNum<[181]>;
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let SubRegIndices = [sub_32] in {
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def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>;
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def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>;
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}
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// FP control registers.
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foreach I = 0-31 in
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def FCR#I : MipsReg<#I, ""#I>;
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// FP condition code registers.
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foreach I = 0-7 in
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def FCC#I : MipsReg<#I, "fcc"#I>;
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// COP2 registers.
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foreach I = 0-31 in
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def COP2#I : MipsReg<#I, ""#I>;
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// PC register
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def PC : Register<"pc">;
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// Hardware register $29
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def HWR29 : MipsReg<29, "29">;
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// Accum registers
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foreach I = 0-3 in
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def AC#I : ACCReg<#I, "ac"#I,
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[!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
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def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
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// DSP-ASE control register fields.
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def DSPPos : Register<"">;
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def DSPSCount : Register<"">;
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def DSPCarry : Register<"">;
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def DSPEFI : Register<"">;
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def DSPOutFlag16_19 : Register<"">;
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def DSPOutFlag20 : Register<"">;
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def DSPOutFlag21 : Register<"">;
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def DSPOutFlag22 : Register<"">;
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def DSPOutFlag23 : Register<"">;
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def DSPCCond : Register<"">;
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let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
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sub_dsp23] in
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def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
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DSPOutFlag21, DSPOutFlag22,
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DSPOutFlag23]>;
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// MSA-ASE control registers.
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def MSAIR : Register<"0">;
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def MSACSR : Register<"1">;
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def MSAAccess : Register<"2">;
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def MSASave : Register<"3">;
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def MSAModify : Register<"4">;
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def MSARequest : Register<"5">;
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def MSAMap : Register<"6">;
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def MSAUnmap : Register<"7">;
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}
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//===----------------------------------------------------------------------===//
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// Register Classes
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//===----------------------------------------------------------------------===//
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class GPR32Class<list<ValueType> regTypes> :
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RegisterClass<"Mips", regTypes, 32, (add
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// Reserved
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ZERO, AT,
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Not preserved across procedure calls
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T0, T1, T2, T3, T4, T5, T6, T7,
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// Callee save
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S0, S1, S2, S3, S4, S5, S6, S7,
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// Not preserved across procedure calls
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T8, T9,
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// Reserved
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K0, K1, GP, SP, FP, RA)>;
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def GPR32 : GPR32Class<[i32]>;
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def DSPR : GPR32Class<[v4i8, v2i16]>;
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def GPR64 : RegisterClass<"Mips", [i64], 64, (add
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// Reserved
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ZERO_64, AT_64,
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// Return Values and Arguments
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V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
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// Not preserved across procedure calls
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T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
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// Callee save
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S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
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// Not preserved across procedure calls
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T8_64, T9_64,
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// Reserved
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K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
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def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Callee save
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S0, S1)>;
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def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Callee save
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S0, S1,
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SP)>;
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def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
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def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
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// 64bit fp:
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// * FGR64 - 32 64-bit registers
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// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
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//
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// 32bit fp:
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// * FGR32 - 16 32-bit even registers
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// * FGR32 - 32 32-bit registers (single float only mode)
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def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
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def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
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Unallocatable;
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def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
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// Return Values and Arguments
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D0, D1,
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// Not preserved across procedure calls
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D2, D3, D4, D5,
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// Return Values and Arguments
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D6, D7,
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// Not preserved across procedure calls
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D8, D9,
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// Callee save
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D10, D11, D12, D13, D14, D15)>;
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def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
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// FP control registers.
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def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
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Unallocatable;
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// FP condition code registers.
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def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
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Unallocatable;
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def MSA128B: RegisterClass<"Mips", [v16i8], 128,
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(sequence "W%u", 0, 31)>;
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def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
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(sequence "W%u", 0, 31)>;
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def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
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(sequence "W%u", 0, 31)>;
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def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
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(sequence "W%u", 0, 31)>;
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def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
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MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
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// Hi/Lo Registers
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def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
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def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
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def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
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def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
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def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
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def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
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// Hardware registers
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def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
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// Accumulator Registers
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def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
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let Size = 64;
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}
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def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
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let Size = 128;
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}
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def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
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let Size = 64;
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}
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def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
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// Coprocessor 2 registers.
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def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
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Unallocatable;
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// Register Operands.
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class MipsAsmRegOperand : AsmOperandClass {
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let RenderMethod = "addRegAsmOperands";
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}
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def GPR32AsmOperand : MipsAsmRegOperand {
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let Name = "GPR32Asm";
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let ParserMethod = "parseGPR32";
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}
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def GPR64AsmOperand : MipsAsmRegOperand {
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let Name = "GPR64Asm";
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let ParserMethod = "parseGPR64";
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}
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def ACC64DSPAsmOperand : MipsAsmRegOperand {
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let Name = "ACC64DSPAsm";
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let ParserMethod = "parseACC64DSP";
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}
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def LO32DSPAsmOperand : MipsAsmRegOperand {
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let Name = "LO32DSPAsm";
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let ParserMethod = "parseLO32DSP";
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}
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def HI32DSPAsmOperand : MipsAsmRegOperand {
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let Name = "HI32DSPAsm";
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let ParserMethod = "parseHI32DSP";
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}
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def CCRAsmOperand : MipsAsmRegOperand {
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let Name = "CCRAsm";
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let ParserMethod = "parseCCRRegs";
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}
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def AFGR64AsmOperand : MipsAsmRegOperand {
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let Name = "AFGR64Asm";
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let ParserMethod = "parseAFGR64Regs";
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}
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def FGR64AsmOperand : MipsAsmRegOperand {
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let Name = "FGR64Asm";
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let ParserMethod = "parseFGR64Regs";
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}
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def FGR32AsmOperand : MipsAsmRegOperand {
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let Name = "FGR32Asm";
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let ParserMethod = "parseFGR32Regs";
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}
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def FGRH32AsmOperand : MipsAsmRegOperand {
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let Name = "FGRH32Asm";
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let ParserMethod = "parseFGRH32Regs";
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}
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def FCCRegsAsmOperand : MipsAsmRegOperand {
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let Name = "FCCRegsAsm";
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let ParserMethod = "parseFCCRegs";
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}
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def MSA128BAsmOperand : MipsAsmRegOperand {
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let Name = "MSA128BAsm";
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let ParserMethod = "parseMSA128BRegs";
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}
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def MSA128HAsmOperand : MipsAsmRegOperand {
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let Name = "MSA128HAsm";
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let ParserMethod = "parseMSA128HRegs";
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}
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def MSA128WAsmOperand : MipsAsmRegOperand {
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let Name = "MSA128WAsm";
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let ParserMethod = "parseMSA128WRegs";
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}
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def MSA128DAsmOperand : MipsAsmRegOperand {
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let Name = "MSA128DAsm";
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let ParserMethod = "parseMSA128DRegs";
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}
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def GPR32Opnd : RegisterOperand<GPR32> {
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let ParserMatchClass = GPR32AsmOperand;
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}
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def GPR64Opnd : RegisterOperand<GPR64> {
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let ParserMatchClass = GPR64AsmOperand;
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}
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def DSPROpnd : RegisterOperand<DSPR> {
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let ParserMatchClass = GPR32AsmOperand;
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}
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def CCROpnd : RegisterOperand<CCR> {
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let ParserMatchClass = CCRAsmOperand;
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}
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def HWRegsAsmOperand : MipsAsmRegOperand {
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let Name = "HWRegsAsm";
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let ParserMethod = "parseHWRegs";
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}
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def COP2AsmOperand : MipsAsmRegOperand {
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let Name = "COP2Asm";
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let ParserMethod = "parseCOP2";
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}
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def HWRegsOpnd : RegisterOperand<HWRegs> {
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let ParserMatchClass = HWRegsAsmOperand;
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}
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def AFGR64Opnd : RegisterOperand<AFGR64> {
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let ParserMatchClass = AFGR64AsmOperand;
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}
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def FGR64Opnd : RegisterOperand<FGR64> {
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let ParserMatchClass = FGR64AsmOperand;
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}
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def FGR32Opnd : RegisterOperand<FGR32> {
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let ParserMatchClass = FGR32AsmOperand;
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}
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def FGRH32Opnd : RegisterOperand<FGRH32> {
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let ParserMatchClass = FGRH32AsmOperand;
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}
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def FCCRegsOpnd : RegisterOperand<FCC> {
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let ParserMatchClass = FCCRegsAsmOperand;
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}
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def LO32DSPOpnd : RegisterOperand<LO32DSP> {
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let ParserMatchClass = LO32DSPAsmOperand;
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}
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def HI32DSPOpnd : RegisterOperand<HI32DSP> {
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let ParserMatchClass = HI32DSPAsmOperand;
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}
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def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
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let ParserMatchClass = ACC64DSPAsmOperand;
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}
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def COP2Opnd : RegisterOperand<COP2> {
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let ParserMatchClass = COP2AsmOperand;
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}
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def MSA128BOpnd : RegisterOperand<MSA128B> {
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let ParserMatchClass = MSA128BAsmOperand;
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}
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def MSA128HOpnd : RegisterOperand<MSA128H> {
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let ParserMatchClass = MSA128HAsmOperand;
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}
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def MSA128WOpnd : RegisterOperand<MSA128W> {
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let ParserMatchClass = MSA128WAsmOperand;
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}
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def MSA128DOpnd : RegisterOperand<MSA128D> {
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let ParserMatchClass = MSA128DAsmOperand;
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}
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