mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207509 91177308-0d34-0410-b5e6-96231b3b80d8
746 lines
27 KiB
C++
746 lines
27 KiB
C++
//===-- ARM64ExpandPseudoInsts.cpp - Expand pseudo instructions ---*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions to allow proper scheduling and other late optimizations. This
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// pass should be run after register allocation but before the post-regalloc
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// scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARM64AddressingModes.h"
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#include "ARM64InstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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class ARM64ExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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ARM64ExpandPseudo() : MachineFunctionPass(ID) {}
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const ARM64InstrInfo *TII;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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const char *getPassName() const override {
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return "ARM64 pseudo instruction expansion pass";
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}
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
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bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned BitSize);
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};
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char ARM64ExpandPseudo::ID = 0;
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}
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/// \brief Transfer implicit operands on the pseudo instruction to the
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/// instructions created from the expansion.
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static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
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MachineInstrBuilder &DefMI) {
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const MCInstrDesc &Desc = OldMI.getDesc();
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for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); i != e;
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++i) {
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const MachineOperand &MO = OldMI.getOperand(i);
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assert(MO.isReg() && MO.getReg());
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if (MO.isUse())
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UseMI.addOperand(MO);
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else
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DefMI.addOperand(MO);
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}
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}
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/// \brief Helper function which extracts the specified 16-bit chunk from a
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/// 64-bit value.
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static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
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assert(ChunkIdx < 4 && "Out of range chunk index specified!");
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return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
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}
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/// \brief Helper function which replicates a 16-bit chunk within a 64-bit
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/// value. Indices correspond to element numbers in a v4i16.
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static uint64_t replicateChunk(uint64_t Imm, unsigned FromIdx, unsigned ToIdx) {
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assert((FromIdx < 4) && (ToIdx < 4) && "Out of range chunk index specified!");
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const unsigned ShiftAmt = ToIdx * 16;
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// Replicate the source chunk to the destination position.
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const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
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// Clear the destination chunk.
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Imm &= ~(0xFFFFLL << ShiftAmt);
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// Insert the replicated chunk.
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return Imm | Chunk;
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}
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/// \brief Helper function which tries to materialize a 64-bit value with an
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/// ORR + MOVK instruction sequence.
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static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const ARM64InstrInfo *TII, unsigned ChunkIdx) {
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assert(ChunkIdx < 4 && "Out of range chunk index specified!");
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const unsigned ShiftAmt = ChunkIdx * 16;
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uint64_t Encoding;
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if (ARM64_AM::processLogicalImmediate(OrrImm, 64, Encoding)) {
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// Create the ORR-immediate instruction.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::ORRXri))
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.addOperand(MI.getOperand(0))
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.addReg(ARM64::XZR)
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.addImm(Encoding);
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// Create the MOVK instruction.
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const unsigned Imm16 = getChunk(UImm, ChunkIdx);
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const unsigned DstReg = MI.getOperand(0).getReg();
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const bool DstIsDead = MI.getOperand(0).isDead();
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MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::MOVKXi))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstReg)
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.addImm(Imm16)
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.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftAmt));
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transferImpOps(MI, MIB, MIB1);
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MI.eraseFromParent();
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return true;
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}
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return false;
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}
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/// \brief Check whether the given 16-bit chunk replicated to full 64-bit width
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/// can be materialized with an ORR instruction.
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static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
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Chunk = (Chunk << 48) | (Chunk << 32) | (Chunk << 16) | Chunk;
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return ARM64_AM::processLogicalImmediate(Chunk, 64, Encoding);
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}
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/// \brief Check for identical 16-bit chunks within the constant and if so
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/// materialize them with a single ORR instruction. The remaining one or two
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/// 16-bit chunks will be materialized with MOVK instructions.
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///
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/// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
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/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
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/// an ORR instruction.
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///
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static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const ARM64InstrInfo *TII) {
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typedef DenseMap<uint64_t, unsigned> CountMap;
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CountMap Counts;
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// Scan the constant and count how often every chunk occurs.
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for (unsigned Idx = 0; Idx < 4; ++Idx)
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++Counts[getChunk(UImm, Idx)];
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// Traverse the chunks to find one which occurs more than once.
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for (CountMap::const_iterator Chunk = Counts.begin(), End = Counts.end();
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Chunk != End; ++Chunk) {
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const uint64_t ChunkVal = Chunk->first;
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const unsigned Count = Chunk->second;
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uint64_t Encoding = 0;
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// We are looking for chunks which have two or three instances and can be
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// materialized with an ORR instruction.
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if ((Count != 2 && Count != 3) || !canUseOrr(ChunkVal, Encoding))
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continue;
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const bool CountThree = Count == 3;
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// Create the ORR-immediate instruction.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::ORRXri))
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.addOperand(MI.getOperand(0))
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.addReg(ARM64::XZR)
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.addImm(Encoding);
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const unsigned DstReg = MI.getOperand(0).getReg();
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const bool DstIsDead = MI.getOperand(0).isDead();
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unsigned ShiftAmt = 0;
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uint64_t Imm16 = 0;
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// Find the first chunk not materialized with the ORR instruction.
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for (; ShiftAmt < 64; ShiftAmt += 16) {
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Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
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if (Imm16 != ChunkVal)
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break;
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}
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// Create the first MOVK instruction.
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MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::MOVKXi))
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.addReg(DstReg,
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RegState::Define | getDeadRegState(DstIsDead && CountThree))
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.addReg(DstReg)
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.addImm(Imm16)
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.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftAmt));
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// In case we have three instances the whole constant is now materialized
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// and we can exit.
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if (CountThree) {
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transferImpOps(MI, MIB, MIB1);
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MI.eraseFromParent();
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return true;
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}
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// Find the remaining chunk which needs to be materialized.
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for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) {
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Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
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if (Imm16 != ChunkVal)
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break;
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}
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// Create the second MOVK instruction.
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MachineInstrBuilder MIB2 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::MOVKXi))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstReg)
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.addImm(Imm16)
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.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftAmt));
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transferImpOps(MI, MIB, MIB2);
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MI.eraseFromParent();
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return true;
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}
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return false;
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}
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/// \brief Check whether this chunk matches the pattern '1...0...'. This pattern
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/// starts a contiguous sequence of ones if we look at the bits from the LSB
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/// towards the MSB.
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static bool isStartChunk(uint64_t Chunk) {
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if (Chunk == 0 || Chunk == UINT64_MAX)
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return false;
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return (CountLeadingOnes_64(Chunk) + countTrailingZeros(Chunk)) == 64;
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}
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/// \brief Check whether this chunk matches the pattern '0...1...' This pattern
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/// ends a contiguous sequence of ones if we look at the bits from the LSB
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/// towards the MSB.
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static bool isEndChunk(uint64_t Chunk) {
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if (Chunk == 0 || Chunk == UINT64_MAX)
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return false;
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return (countLeadingZeros(Chunk) + CountTrailingOnes_64(Chunk)) == 64;
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}
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/// \brief Clear or set all bits in the chunk at the given index.
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static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
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const uint64_t Mask = 0xFFFF;
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if (Clear)
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// Clear chunk in the immediate.
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Imm &= ~(Mask << (Idx * 16));
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else
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// Set all bits in the immediate for the particular chunk.
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Imm |= Mask << (Idx * 16);
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return Imm;
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}
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/// \brief Check whether the constant contains a sequence of contiguous ones,
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/// which might be interrupted by one or two chunks. If so, materialize the
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/// sequence of contiguous ones with an ORR instruction.
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/// Materialize the chunks which are either interrupting the sequence or outside
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/// of the sequence with a MOVK instruction.
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///
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/// Assuming S is a chunk which starts the sequence (1...0...), E is a chunk
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/// which ends the sequence (0...1...). Then we are looking for constants which
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/// contain at least one S and E chunk.
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/// E.g. |E|A|B|S|, |A|E|B|S| or |A|B|E|S|.
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///
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/// We are also looking for constants like |S|A|B|E| where the contiguous
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/// sequence of ones wraps around the MSB into the LSB.
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///
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static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const ARM64InstrInfo *TII) {
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const int NotSet = -1;
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const uint64_t Mask = 0xFFFF;
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int StartIdx = NotSet;
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int EndIdx = NotSet;
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// Try to find the chunks which start/end a contiguous sequence of ones.
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for (int Idx = 0; Idx < 4; ++Idx) {
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int64_t Chunk = getChunk(UImm, Idx);
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// Sign extend the 16-bit chunk to 64-bit.
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Chunk = (Chunk << 48) >> 48;
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if (isStartChunk(Chunk))
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StartIdx = Idx;
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else if (isEndChunk(Chunk))
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EndIdx = Idx;
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}
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// Early exit in case we can't find a start/end chunk.
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if (StartIdx == NotSet || EndIdx == NotSet)
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return false;
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// Outside of the contiguous sequence of ones everything needs to be zero.
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uint64_t Outside = 0;
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// Chunks between the start and end chunk need to have all their bits set.
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uint64_t Inside = Mask;
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// If our contiguous sequence of ones wraps around from the MSB into the LSB,
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// just swap indices and pretend we are materializing a contiguous sequence
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// of zeros surrounded by a contiguous sequence of ones.
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if (StartIdx > EndIdx) {
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std::swap(StartIdx, EndIdx);
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std::swap(Outside, Inside);
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}
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uint64_t OrrImm = UImm;
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int FirstMovkIdx = NotSet;
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int SecondMovkIdx = NotSet;
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// Find out which chunks we need to patch up to obtain a contiguous sequence
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// of ones.
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for (int Idx = 0; Idx < 4; ++Idx) {
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const uint64_t Chunk = getChunk(UImm, Idx);
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// Check whether we are looking at a chunk which is not part of the
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// contiguous sequence of ones.
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if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) {
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OrrImm = updateImm(OrrImm, Idx, Outside == 0);
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// Remember the index we need to patch.
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if (FirstMovkIdx == NotSet)
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FirstMovkIdx = Idx;
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else
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SecondMovkIdx = Idx;
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// Check whether we are looking a chunk which is part of the contiguous
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// sequence of ones.
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} else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) {
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OrrImm = updateImm(OrrImm, Idx, Inside != Mask);
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// Remember the index we need to patch.
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if (FirstMovkIdx == NotSet)
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FirstMovkIdx = Idx;
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else
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SecondMovkIdx = Idx;
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}
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}
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assert(FirstMovkIdx != NotSet && "Constant materializable with single ORR!");
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// Create the ORR-immediate instruction.
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uint64_t Encoding = 0;
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ARM64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::ORRXri))
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.addOperand(MI.getOperand(0))
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.addReg(ARM64::XZR)
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.addImm(Encoding);
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const unsigned DstReg = MI.getOperand(0).getReg();
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const bool DstIsDead = MI.getOperand(0).isDead();
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const bool SingleMovk = SecondMovkIdx == NotSet;
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// Create the first MOVK instruction.
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MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::MOVKXi))
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.addReg(DstReg,
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RegState::Define | getDeadRegState(DstIsDead && SingleMovk))
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.addReg(DstReg)
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.addImm(getChunk(UImm, FirstMovkIdx))
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.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, FirstMovkIdx * 16));
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// Early exit in case we only need to emit a single MOVK instruction.
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if (SingleMovk) {
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transferImpOps(MI, MIB, MIB1);
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MI.eraseFromParent();
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return true;
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}
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// Create the second MOVK instruction.
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MachineInstrBuilder MIB2 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::MOVKXi))
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.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(DstReg)
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.addImm(getChunk(UImm, SecondMovkIdx))
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.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, SecondMovkIdx * 16));
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transferImpOps(MI, MIB, MIB2);
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MI.eraseFromParent();
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return true;
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}
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/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
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/// real move-immediate instructions to synthesize the immediate.
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bool ARM64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned BitSize) {
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MachineInstr &MI = *MBBI;
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uint64_t Imm = MI.getOperand(1).getImm();
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const unsigned Mask = 0xFFFF;
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// Try a MOVI instruction (aka ORR-immediate with the zero register).
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uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
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uint64_t Encoding;
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if (ARM64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
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unsigned Opc = (BitSize == 32 ? ARM64::ORRWri : ARM64::ORRXri);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
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.addOperand(MI.getOperand(0))
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.addReg(BitSize == 32 ? ARM64::WZR : ARM64::XZR)
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.addImm(Encoding);
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transferImpOps(MI, MIB, MIB);
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MI.eraseFromParent();
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return true;
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}
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// Scan the immediate and count the number of 16-bit chunks which are either
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// all ones or all zeros.
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unsigned OneChunks = 0;
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unsigned ZeroChunks = 0;
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for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
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const unsigned Chunk = (Imm >> Shift) & Mask;
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if (Chunk == Mask)
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OneChunks++;
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else if (Chunk == 0)
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ZeroChunks++;
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}
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// Since we can't materialize the constant with a single ORR instruction,
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// let's see whether we can materialize 3/4 of the constant with an ORR
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// instruction and use an additional MOVK instruction to materialize the
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// remaining 1/4.
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//
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// We are looking for constants with a pattern like: |A|X|B|X| or |X|A|X|B|.
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//
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// E.g. assuming |A|X|A|X| is a pattern which can be materialized with ORR,
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// we would create the following instruction sequence:
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//
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// ORR x0, xzr, |A|X|A|X|
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// MOVK x0, |B|, LSL #16
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//
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// Only look at 64-bit constants which can't be materialized with a single
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// instruction e.g. which have less than either three all zero or all one
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// chunks.
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//
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// Ignore 32-bit constants here, they always can be materialized with a
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// MOVZ/MOVN + MOVK pair. Since the 32-bit constant can't be materialized
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// with a single ORR, the best sequence we can achieve is a ORR + MOVK pair.
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// Thus we fall back to the default code below which in the best case creates
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// a single MOVZ/MOVN instruction (in case one chunk is all zero or all one).
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//
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if (BitSize == 64 && OneChunks < 3 && ZeroChunks < 3) {
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// If we interpret the 64-bit constant as a v4i16, are elements 0 and 2
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// identical?
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if (getChunk(UImm, 0) == getChunk(UImm, 2)) {
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// See if we can come up with a constant which can be materialized with
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// ORR-immediate by replicating element 3 into element 1.
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uint64_t OrrImm = replicateChunk(UImm, 3, 1);
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if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 1))
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return true;
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// See if we can come up with a constant which can be materialized with
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// ORR-immediate by replicating element 1 into element 3.
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OrrImm = replicateChunk(UImm, 1, 3);
|
|
if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 3))
|
|
return true;
|
|
|
|
// If we interpret the 64-bit constant as a v4i16, are elements 1 and 3
|
|
// identical?
|
|
} else if (getChunk(UImm, 1) == getChunk(UImm, 3)) {
|
|
// See if we can come up with a constant which can be materialized with
|
|
// ORR-immediate by replicating element 2 into element 0.
|
|
uint64_t OrrImm = replicateChunk(UImm, 2, 0);
|
|
if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 0))
|
|
return true;
|
|
|
|
// See if we can come up with a constant which can be materialized with
|
|
// ORR-immediate by replicating element 1 into element 3.
|
|
OrrImm = replicateChunk(UImm, 0, 2);
|
|
if (tryOrrMovk(UImm, OrrImm, MI, MBB, MBBI, TII, 2))
|
|
return true;
|
|
}
|
|
}
|
|
|
|
// Check for identical 16-bit chunks within the constant and if so materialize
|
|
// them with a single ORR instruction. The remaining one or two 16-bit chunks
|
|
// will be materialized with MOVK instructions.
|
|
if (BitSize == 64 && tryToreplicateChunks(UImm, MI, MBB, MBBI, TII))
|
|
return true;
|
|
|
|
// Check whether the constant contains a sequence of contiguous ones, which
|
|
// might be interrupted by one or two chunks. If so, materialize the sequence
|
|
// of contiguous ones with an ORR instruction. Materialize the chunks which
|
|
// are either interrupting the sequence or outside of the sequence with a
|
|
// MOVK instruction.
|
|
if (BitSize == 64 && trySequenceOfOnes(UImm, MI, MBB, MBBI, TII))
|
|
return true;
|
|
|
|
// Use a MOVZ or MOVN instruction to set the high bits, followed by one or
|
|
// more MOVK instructions to insert additional 16-bit portions into the
|
|
// lower bits.
|
|
bool isNeg = false;
|
|
|
|
// Use MOVN to materialize the high bits if we have more all one chunks
|
|
// than all zero chunks.
|
|
if (OneChunks > ZeroChunks) {
|
|
isNeg = true;
|
|
Imm = ~Imm;
|
|
}
|
|
|
|
unsigned FirstOpc;
|
|
if (BitSize == 32) {
|
|
Imm &= (1LL << 32) - 1;
|
|
FirstOpc = (isNeg ? ARM64::MOVNWi : ARM64::MOVZWi);
|
|
} else {
|
|
FirstOpc = (isNeg ? ARM64::MOVNXi : ARM64::MOVZXi);
|
|
}
|
|
unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
|
|
unsigned LastShift = 0; // LSL amount for last MOVK
|
|
if (Imm != 0) {
|
|
unsigned LZ = countLeadingZeros(Imm);
|
|
unsigned TZ = countTrailingZeros(Imm);
|
|
Shift = ((63 - LZ) / 16) * 16;
|
|
LastShift = (TZ / 16) * 16;
|
|
}
|
|
unsigned Imm16 = (Imm >> Shift) & Mask;
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
bool DstIsDead = MI.getOperand(0).isDead();
|
|
MachineInstrBuilder MIB1 =
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
|
|
.addReg(DstReg, RegState::Define |
|
|
getDeadRegState(DstIsDead && Shift == LastShift))
|
|
.addImm(Imm16)
|
|
.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, Shift));
|
|
|
|
// If a MOVN was used for the high bits of a negative value, flip the rest
|
|
// of the bits back for use with MOVK.
|
|
if (isNeg)
|
|
Imm = ~Imm;
|
|
|
|
if (Shift == LastShift) {
|
|
transferImpOps(MI, MIB1, MIB1);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
MachineInstrBuilder MIB2;
|
|
unsigned Opc = (BitSize == 32 ? ARM64::MOVKWi : ARM64::MOVKXi);
|
|
while (Shift != LastShift) {
|
|
Shift -= 16;
|
|
Imm16 = (Imm >> Shift) & Mask;
|
|
if (Imm16 == (isNeg ? Mask : 0))
|
|
continue; // This 16-bit portion is already set correctly.
|
|
MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
|
|
.addReg(DstReg,
|
|
RegState::Define |
|
|
getDeadRegState(DstIsDead && Shift == LastShift))
|
|
.addReg(DstReg)
|
|
.addImm(Imm16)
|
|
.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, Shift));
|
|
}
|
|
|
|
transferImpOps(MI, MIB1, MIB2);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
/// \brief If MBBI references a pseudo instruction that should be expanded here,
|
|
/// do the expansion and return true. Otherwise return false.
|
|
bool ARM64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI) {
|
|
MachineInstr &MI = *MBBI;
|
|
unsigned Opcode = MI.getOpcode();
|
|
switch (Opcode) {
|
|
default:
|
|
break;
|
|
|
|
case ARM64::ADDWrr:
|
|
case ARM64::SUBWrr:
|
|
case ARM64::ADDXrr:
|
|
case ARM64::SUBXrr:
|
|
case ARM64::ADDSWrr:
|
|
case ARM64::SUBSWrr:
|
|
case ARM64::ADDSXrr:
|
|
case ARM64::SUBSXrr:
|
|
case ARM64::ANDWrr:
|
|
case ARM64::ANDXrr:
|
|
case ARM64::BICWrr:
|
|
case ARM64::BICXrr:
|
|
case ARM64::ANDSWrr:
|
|
case ARM64::ANDSXrr:
|
|
case ARM64::BICSWrr:
|
|
case ARM64::BICSXrr:
|
|
case ARM64::EONWrr:
|
|
case ARM64::EONXrr:
|
|
case ARM64::EORWrr:
|
|
case ARM64::EORXrr:
|
|
case ARM64::ORNWrr:
|
|
case ARM64::ORNXrr:
|
|
case ARM64::ORRWrr:
|
|
case ARM64::ORRXrr: {
|
|
unsigned Opcode;
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return false;
|
|
case ARM64::ADDWrr: Opcode = ARM64::ADDWrs; break;
|
|
case ARM64::SUBWrr: Opcode = ARM64::SUBWrs; break;
|
|
case ARM64::ADDXrr: Opcode = ARM64::ADDXrs; break;
|
|
case ARM64::SUBXrr: Opcode = ARM64::SUBXrs; break;
|
|
case ARM64::ADDSWrr: Opcode = ARM64::ADDSWrs; break;
|
|
case ARM64::SUBSWrr: Opcode = ARM64::SUBSWrs; break;
|
|
case ARM64::ADDSXrr: Opcode = ARM64::ADDSXrs; break;
|
|
case ARM64::SUBSXrr: Opcode = ARM64::SUBSXrs; break;
|
|
case ARM64::ANDWrr: Opcode = ARM64::ANDWrs; break;
|
|
case ARM64::ANDXrr: Opcode = ARM64::ANDXrs; break;
|
|
case ARM64::BICWrr: Opcode = ARM64::BICWrs; break;
|
|
case ARM64::BICXrr: Opcode = ARM64::BICXrs; break;
|
|
case ARM64::ANDSWrr: Opcode = ARM64::ANDSWrs; break;
|
|
case ARM64::ANDSXrr: Opcode = ARM64::ANDSXrs; break;
|
|
case ARM64::BICSWrr: Opcode = ARM64::BICSWrs; break;
|
|
case ARM64::BICSXrr: Opcode = ARM64::BICSXrs; break;
|
|
case ARM64::EONWrr: Opcode = ARM64::EONWrs; break;
|
|
case ARM64::EONXrr: Opcode = ARM64::EONXrs; break;
|
|
case ARM64::EORWrr: Opcode = ARM64::EORWrs; break;
|
|
case ARM64::EORXrr: Opcode = ARM64::EORXrs; break;
|
|
case ARM64::ORNWrr: Opcode = ARM64::ORNWrs; break;
|
|
case ARM64::ORNXrr: Opcode = ARM64::ORNXrs; break;
|
|
case ARM64::ORRWrr: Opcode = ARM64::ORRWrs; break;
|
|
case ARM64::ORRXrr: Opcode = ARM64::ORRXrs; break;
|
|
}
|
|
MachineInstrBuilder MIB1 =
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
|
|
MI.getOperand(0).getReg())
|
|
.addOperand(MI.getOperand(1))
|
|
.addOperand(MI.getOperand(2))
|
|
.addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
|
|
transferImpOps(MI, MIB1, MIB1);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
case ARM64::FCVTSHpseudo: {
|
|
MachineOperand Src = MI.getOperand(1);
|
|
Src.setImplicit();
|
|
unsigned SrcH = TII->getRegisterInfo().getSubReg(Src.getReg(), ARM64::hsub);
|
|
auto MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::FCVTSHr))
|
|
.addOperand(MI.getOperand(0))
|
|
.addReg(SrcH, RegState::Undef)
|
|
.addOperand(Src);
|
|
transferImpOps(MI, MIB, MIB);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
case ARM64::LOADgot: {
|
|
// Expand into ADRP + LDR.
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
const MachineOperand &MO1 = MI.getOperand(1);
|
|
unsigned Flags = MO1.getTargetFlags();
|
|
MachineInstrBuilder MIB1 =
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::ADRP), DstReg);
|
|
MachineInstrBuilder MIB2 =
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::LDRXui))
|
|
.addOperand(MI.getOperand(0))
|
|
.addReg(DstReg);
|
|
|
|
if (MO1.isGlobal()) {
|
|
MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | ARM64II::MO_PAGE);
|
|
MIB2.addGlobalAddress(MO1.getGlobal(), 0,
|
|
Flags | ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
|
|
} else if (MO1.isSymbol()) {
|
|
MIB1.addExternalSymbol(MO1.getSymbolName(), Flags | ARM64II::MO_PAGE);
|
|
MIB2.addExternalSymbol(MO1.getSymbolName(),
|
|
Flags | ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
|
|
} else {
|
|
assert(MO1.isCPI() &&
|
|
"Only expect globals, externalsymbols, or constant pools");
|
|
MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
|
|
Flags | ARM64II::MO_PAGE);
|
|
MIB2.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
|
|
Flags | ARM64II::MO_PAGEOFF | ARM64II::MO_NC);
|
|
}
|
|
|
|
transferImpOps(MI, MIB1, MIB2);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
case ARM64::MOVaddr:
|
|
case ARM64::MOVaddrJT:
|
|
case ARM64::MOVaddrCP:
|
|
case ARM64::MOVaddrBA:
|
|
case ARM64::MOVaddrTLS:
|
|
case ARM64::MOVaddrEXT: {
|
|
// Expand into ADRP + ADD.
|
|
unsigned DstReg = MI.getOperand(0).getReg();
|
|
MachineInstrBuilder MIB1 =
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::ADRP), DstReg)
|
|
.addOperand(MI.getOperand(1));
|
|
|
|
MachineInstrBuilder MIB2 =
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::ADDXri))
|
|
.addOperand(MI.getOperand(0))
|
|
.addReg(DstReg)
|
|
.addOperand(MI.getOperand(2))
|
|
.addImm(0);
|
|
|
|
transferImpOps(MI, MIB1, MIB2);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
case ARM64::MOVi32imm:
|
|
return expandMOVImm(MBB, MBBI, 32);
|
|
case ARM64::MOVi64imm:
|
|
return expandMOVImm(MBB, MBBI, 64);
|
|
case ARM64::RET_ReallyLR:
|
|
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::RET))
|
|
.addReg(ARM64::LR);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// \brief Iterate over the instructions in basic block MBB and expand any
|
|
/// pseudo instructions. Return true if anything was modified.
|
|
bool ARM64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
while (MBBI != E) {
|
|
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
|
|
Modified |= expandMI(MBB, MBBI);
|
|
MBBI = NMBBI;
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool ARM64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
|
|
TII = static_cast<const ARM64InstrInfo *>(MF.getTarget().getInstrInfo());
|
|
|
|
bool Modified = false;
|
|
for (auto &MBB : MF)
|
|
Modified |= expandMBB(MBB);
|
|
return Modified;
|
|
}
|
|
|
|
/// \brief Returns an instance of the pseudo instruction expansion pass.
|
|
FunctionPass *llvm::createARM64ExpandPseudoPass() {
|
|
return new ARM64ExpandPseudo();
|
|
}
|