mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bd24b33e57
We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207661 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.6 KiB
CMake
57 lines
1.6 KiB
CMake
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
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tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
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tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
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tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
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add_public_tablegen_target(AMDGPUCommonTableGen)
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add_llvm_target(R600CodeGen
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AMDILCFGStructurizer.cpp
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AMDILIntrinsicInfo.cpp
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AMDILISelLowering.cpp
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AMDGPUAsmPrinter.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUISelDAGToDAG.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUSubtarget.cpp
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AMDGPUTargetMachine.cpp
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AMDGPUTargetTransformInfo.cpp
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AMDGPUISelLowering.cpp
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AMDGPUConvertToISA.cpp
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AMDGPUInstrInfo.cpp
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AMDGPURegisterInfo.cpp
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrInfo.cpp
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600TextureIntrinsicsReplacer.cpp
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SIAnnotateControlFlow.cpp
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SIFixSGPRCopies.cpp
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SIInsertWaits.cpp
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SIInstrInfo.cpp
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SIISelLowering.cpp
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
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SIMachineFunctionInfo.cpp
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SIRegisterInfo.cpp
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SITypeRewriter.cpp
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)
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add_subdirectory(InstPrinter)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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