mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b6831cb044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76041 91177308-0d34-0410-b5e6-96231b3b80d8
307 lines
11 KiB
TableGen
307 lines
11 KiB
TableGen
//=====- SystemZOperands.td - SystemZ Operands defs ---------*- tblgen-*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the various SystemZ instruction operands.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff.
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//===----------------------------------------------------------------------===//
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// SystemZ specific condition code. These correspond to CondCode in
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// SystemZ.h. They must be kept in synch.
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def SYSTEMZ_COND_O : PatLeaf<(i8 0)>;
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def SYSTEMZ_COND_H : PatLeaf<(i8 1)>;
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def SYSTEMZ_COND_NLE : PatLeaf<(i8 2)>;
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def SYSTEMZ_COND_L : PatLeaf<(i8 3)>;
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def SYSTEMZ_COND_NHE : PatLeaf<(i8 4)>;
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def SYSTEMZ_COND_LH : PatLeaf<(i8 5)>;
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def SYSTEMZ_COND_NE : PatLeaf<(i8 6)>;
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def SYSTEMZ_COND_E : PatLeaf<(i8 7)>;
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def SYSTEMZ_COND_NLH : PatLeaf<(i8 8)>;
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def SYSTEMZ_COND_HE : PatLeaf<(i8 9)>;
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def SYSTEMZ_COND_NL : PatLeaf<(i8 10)>;
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def SYSTEMZ_COND_LE : PatLeaf<(i8 11)>;
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def SYSTEMZ_COND_NH : PatLeaf<(i8 12)>;
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def SYSTEMZ_COND_NO : PatLeaf<(i8 13)>;
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def LO8 : SDNodeXForm<imm, [{
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// Transformation function: return low 8 bits.
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return getI8Imm(N->getZExtValue() & 0x00000000000000FFULL);
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}]>;
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def LL16 : SDNodeXForm<imm, [{
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// Transformation function: return low 16 bits.
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return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
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}]>;
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def LH16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 16-31.
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return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
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}]>;
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def HL16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-47.
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return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
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}]>;
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def HH16 : SDNodeXForm<imm, [{
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// Transformation function: return bits 48-63.
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return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
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}]>;
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def LO32 : SDNodeXForm<imm, [{
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// Transformation function: return low 32 bits.
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return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
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}]>;
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def HI32 : SDNodeXForm<imm, [{
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// Transformation function: return bits 32-63.
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return getI32Imm(N->getZExtValue() >> 32);
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}]>;
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def i32ll16 : PatLeaf<(i32 imm), [{
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// i32ll16 predicate - true if the 32-bit immediate has only rightmost 16
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// bits set.
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return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
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}], LL16>;
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def i32lh16 : PatLeaf<(i32 imm), [{
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// i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set.
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return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
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}], LH16>;
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def i32ll16c : PatLeaf<(i32 imm), [{
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// i32ll16c predicate - true if the 32-bit immediate has all bits 16-31 set.
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return ((N->getZExtValue() | 0x00000000FFFF0000ULL) == N->getZExtValue());
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}], LL16>;
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def i32lh16c : PatLeaf<(i32 imm), [{
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// i32lh16c predicate - true if the 32-bit immediate has all rightmost 16
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// bits set.
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return ((N->getZExtValue() | 0x000000000000FFFFULL) == N->getZExtValue());
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}], LH16>;
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def i64ll16 : PatLeaf<(i64 imm), [{
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// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
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// bits set.
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return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
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}], LL16>;
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def i64lh16 : PatLeaf<(i64 imm), [{
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// i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
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return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
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}], LH16>;
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def i64hl16 : PatLeaf<(i64 imm), [{
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// i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
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return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
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}], HL16>;
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def i64hh16 : PatLeaf<(i64 imm), [{
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// i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
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return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
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}], HH16>;
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def i64ll16c : PatLeaf<(i64 imm), [{
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// i64ll16c predicate - true if the 64-bit immediate has only rightmost 16
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// bits set.
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return ((N->getZExtValue() | 0xFFFFFFFFFFFF0000ULL) == N->getZExtValue());
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}], LL16>;
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def i64lh16c : PatLeaf<(i64 imm), [{
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// i64lh16c predicate - true if the 64-bit immediate has only bits 16-31 set.
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return ((N->getZExtValue() | 0xFFFFFFFF0000FFFFULL) == N->getZExtValue());
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}], LH16>;
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def i64hl16c : PatLeaf<(i64 imm), [{
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// i64hl16c predicate - true if the 64-bit immediate has only bits 32-47 set.
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return ((N->getZExtValue() | 0xFFFF0000FFFFFFFFULL) == N->getZExtValue());
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}], HL16>;
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def i64hh16c : PatLeaf<(i64 imm), [{
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// i64hh16c predicate - true if the 64-bit immediate has only bits 48-63 set.
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return ((N->getZExtValue() | 0x0000FFFFFFFFFFFFULL) == N->getZExtValue());
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}], HH16>;
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def immSExt16 : PatLeaf<(imm), [{
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// immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
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// field.
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if (N->getValueType(0) == MVT::i64) {
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int16_t)val);
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} else if (N->getValueType(0) == MVT::i32) {
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uint32_t val = N->getZExtValue();
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return ((int32_t)val == (int16_t)val);
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}
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return false;
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}], LL16>;
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def immSExt32 : PatLeaf<(i64 imm), [{
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// immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
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// field.
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uint64_t val = N->getZExtValue();
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return ((int64_t)val == (int32_t)val);
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}], LO32>;
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def i64lo32 : PatLeaf<(i64 imm), [{
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// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
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// bits set.
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return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
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}], LO32>;
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def i64hi32 : PatLeaf<(i64 imm), [{
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// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
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return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
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}], HI32>;
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def i64lo32c : PatLeaf<(i64 imm), [{
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// i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
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// bits set.
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return ((N->getZExtValue() | 0xFFFFFFFF00000000ULL) == N->getZExtValue());
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}], LO32>;
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def i64hi32c : PatLeaf<(i64 imm), [{
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// i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
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return ((N->getZExtValue() | 0x00000000FFFFFFFFULL) == N->getZExtValue());
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}], HI32>;
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def i32immSExt8 : PatLeaf<(i32 imm), [{
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// i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
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// sign extended field.
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return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
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}], LO8>;
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def i32immSExt16 : PatLeaf<(i32 imm), [{
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// i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
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// sign extended field.
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return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
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}], LL16>;
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def i64immSExt32 : PatLeaf<(i64 imm), [{
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
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}], LO32>;
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def i64immZExt32 : PatLeaf<(i64 imm), [{
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// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// zero extended field.
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return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
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}], LO32>;
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// extloads
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def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
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def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
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def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
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def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
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def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
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def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
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def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
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def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
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def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
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def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
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def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
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def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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// A couple of more descriptive operand definitions.
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// 32-bits but only 8 bits are significant.
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def i32i8imm : Operand<i32>;
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// 32-bits but only 16 bits are significant.
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def i32i16imm : Operand<i32>;
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// 64-bits but only 32 bits are significant.
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def i64i32imm : Operand<i64>;
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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// Unsigned i12
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def u12imm : Operand<i32> {
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let PrintMethod = "printU12ImmOperand";
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}
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def u12imm64 : Operand<i64> {
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let PrintMethod = "printU12ImmOperand";
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}
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// Signed i16
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def s16imm : Operand<i32> {
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let PrintMethod = "printS16ImmOperand";
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}
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def s16imm64 : Operand<i64> {
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let PrintMethod = "printS16ImmOperand";
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}
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// Signed i20
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def s20imm : Operand<i32> {
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let PrintMethod = "printS20ImmOperand";
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}
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def s20imm64 : Operand<i64> {
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let PrintMethod = "printS20ImmOperand";
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}
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// Signed i32
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def s32imm : Operand<i32> {
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let PrintMethod = "printS32ImmOperand";
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}
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def s32imm64 : Operand<i64> {
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let PrintMethod = "printS32ImmOperand";
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}
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def imm_pcrel : Operand<i64> {
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let PrintMethod = "printPCRelImmOperand";
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}
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//===----------------------------------------------------------------------===//
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// SystemZ Operand Definitions.
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//===----------------------------------------------------------------------===//
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// Address operands
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// riaddr := reg + imm
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def riaddr32 : Operand<i64>,
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ComplexPattern<i64, 2, "SelectAddrRI12Only", []> {
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let PrintMethod = "printRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, u12imm:$disp);
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}
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def riaddr12 : Operand<i64>,
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ComplexPattern<i64, 2, "SelectAddrRI12", []> {
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let PrintMethod = "printRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp);
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}
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def riaddr : Operand<i64>,
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ComplexPattern<i64, 2, "SelectAddrRI", []> {
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let PrintMethod = "printRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp);
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}
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//===----------------------------------------------------------------------===//
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// rriaddr := reg + reg + imm
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def rriaddr12 : Operand<i64>,
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ComplexPattern<i64, 3, "SelectAddrRRI12", [], []> {
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let PrintMethod = "printRRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp, ADDR64:$index);
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}
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def rriaddr : Operand<i64>,
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ComplexPattern<i64, 3, "SelectAddrRRI20", [], []> {
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let PrintMethod = "printRRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
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}
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def laaddr : Operand<i64>,
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ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
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let PrintMethod = "printRRIAddrOperand";
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let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
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}
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