mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7248968fa5
This is the next big chunk of fast-isel code. The primary purpose is to implement selection of loads and stores, but there is a lot of drag-along to support this. The common code to analyze addresses for both loads and stores is substantial. It's also necessary to add the materialization code for global values. Related to load-store processing is the code to fold loads into integer extends, since otherwise we generate lots of redundant instructions. We also need to add some overrides to some FastEmit routines to ensure we don't assign GPR 0 to a virtual register when this would change the meaning of an instruction. I added handling selection of a few binary arithmetic instructions, to enable committing some test cases I wrote a while back. Finally, ap couple of miscellaneous changes: * I cleaned up some poor style from a previous patch in PPCISelLowering.cpp, pointed out by David Blaikie. * I enlarged the Addr.Offset field to avoid sign problems with 32-bit offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189636 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
2.7 KiB
LLVM
138 lines
2.7 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; Test add with non-legal types
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define void @add_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ELF64: add_i8
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, %b
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; ELF64: add
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i8_imm(i8 %a) nounwind ssp {
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entry:
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; ELF64: add_i8_imm
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, 22;
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; ELF64: addi
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ELF64: add_i16
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, %b
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; ELF64: add
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @add_i16_imm(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ELF64: add_i16_imm
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, 243;
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; ELF64: addi
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test or with non-legal types
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define void @or_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ELF64: or_i8
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, %b
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; ELF64: or
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i8_imm(i8 %a) nounwind ssp {
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entry:
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; ELF64: or_i8_imm
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, -13;
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; ELF64: ori
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ELF64: or_i16
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, %b
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; ELF64: or
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @or_i16_imm(i16 %a) nounwind ssp {
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entry:
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; ELF64: or_i16_imm
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, 273;
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; ELF64: ori
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test sub with non-legal types
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define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ELF64: sub_i8
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, %b
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; ELF64: subf
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i8_imm(i8 %a) nounwind ssp {
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entry:
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; ELF64: sub_i8_imm
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, 22;
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; ELF64: addi
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ELF64: sub_i16
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, %b
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; ELF64: subf
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @sub_i16_imm(i16 %a) nounwind ssp {
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entry:
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; ELF64: sub_i16_imm
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, 247;
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; ELF64: addi
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @sub_i16_badimm(i16 %a) nounwind ssp {
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entry:
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; ELF64: sub_i16_imm
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, -32768;
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; ELF64: subf
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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