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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147089 91177308-0d34-0410-b5e6-96231b3b80d8
212 lines
6.7 KiB
C++
212 lines
6.7 KiB
C++
//===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// LiveIntervalUnion represents a coalesced set of live intervals. This may be
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// used during coalescing to represent a congruence class, or during register
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// allocation to model liveness of a physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveIntervalUnion.h"
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#include "llvm/ADT/SparseBitVector.h"
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#include "llvm/CodeGen/MachineLoopRanges.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <algorithm>
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using namespace llvm;
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// Merge a LiveInterval's segments. Guarantee no overlaps.
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void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
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if (VirtReg.empty())
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return;
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++Tag;
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// Insert each of the virtual register's live segments into the map.
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LiveInterval::iterator RegPos = VirtReg.begin();
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LiveInterval::iterator RegEnd = VirtReg.end();
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SegmentIter SegPos = Segments.find(RegPos->start);
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while (SegPos.valid()) {
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SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
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if (++RegPos == RegEnd)
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return;
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SegPos.advanceTo(RegPos->start);
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}
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// We have reached the end of Segments, so it is no longer necessary to search
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// for the insertion position.
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// It is faster to insert the end first.
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--RegEnd;
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SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
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for (; RegPos != RegEnd; ++RegPos, ++SegPos)
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SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
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}
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// Remove a live virtual register's segments from this union.
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void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
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if (VirtReg.empty())
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return;
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++Tag;
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// Remove each of the virtual register's live segments from the map.
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LiveInterval::iterator RegPos = VirtReg.begin();
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LiveInterval::iterator RegEnd = VirtReg.end();
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SegmentIter SegPos = Segments.find(RegPos->start);
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for (;;) {
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assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
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SegPos.erase();
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if (!SegPos.valid())
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return;
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// Skip all segments that may have been coalesced.
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RegPos = VirtReg.advanceTo(RegPos, SegPos.start());
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if (RegPos == RegEnd)
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return;
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SegPos.advanceTo(RegPos->start);
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}
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}
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void
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LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
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OS << "LIU " << PrintReg(RepReg, TRI);
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if (empty()) {
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OS << " empty\n";
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return;
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}
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for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
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OS << " [" << SI.start() << ' ' << SI.stop() << "):"
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<< PrintReg(SI.value()->reg, TRI);
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}
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OS << '\n';
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}
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#ifndef NDEBUG
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// Verify the live intervals in this union and add them to the visited set.
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void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
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for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI)
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VisitedVRegs.set(SI.value()->reg);
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}
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#endif //!NDEBUG
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// Scan the vector of interfering virtual registers in this union. Assume it's
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// quite small.
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bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
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SmallVectorImpl<LiveInterval*>::const_iterator I =
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std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
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return I != InterferingVRegs.end();
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}
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// Collect virtual registers in this union that interfere with this
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// query's live virtual register.
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//
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// The query state is one of:
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//
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// 1. CheckedFirstInterference == false: Iterators are uninitialized.
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// 2. SeenAllInterferences == true: InterferingVRegs complete, iterators unused.
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// 3. Iterators left at the last seen intersection.
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//
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unsigned LiveIntervalUnion::Query::
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collectInterferingVRegs(unsigned MaxInterferingRegs) {
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// Fast path return if we already have the desired information.
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if (SeenAllInterferences || InterferingVRegs.size() >= MaxInterferingRegs)
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return InterferingVRegs.size();
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// Set up iterators on the first call.
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if (!CheckedFirstInterference) {
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CheckedFirstInterference = true;
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// Quickly skip interference check for empty sets.
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if (VirtReg->empty() || LiveUnion->empty()) {
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SeenAllInterferences = true;
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return 0;
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}
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// In most cases, the union will start before VirtReg.
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VirtRegI = VirtReg->begin();
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LiveUnionI.setMap(LiveUnion->getMap());
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LiveUnionI.find(VirtRegI->start);
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}
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LiveInterval::iterator VirtRegEnd = VirtReg->end();
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LiveInterval *RecentReg = 0;
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while (LiveUnionI.valid()) {
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assert(VirtRegI != VirtRegEnd && "Reached end of VirtReg");
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// Check for overlapping interference.
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while (VirtRegI->start < LiveUnionI.stop() &&
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VirtRegI->end > LiveUnionI.start()) {
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// This is an overlap, record the interfering register.
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LiveInterval *VReg = LiveUnionI.value();
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if (VReg != RecentReg && !isSeenInterference(VReg)) {
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RecentReg = VReg;
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InterferingVRegs.push_back(VReg);
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if (InterferingVRegs.size() >= MaxInterferingRegs)
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return InterferingVRegs.size();
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}
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// This LiveUnion segment is no longer interesting.
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if (!(++LiveUnionI).valid()) {
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SeenAllInterferences = true;
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return InterferingVRegs.size();
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}
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}
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// The iterators are now not overlapping, LiveUnionI has been advanced
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// beyond VirtRegI.
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assert(VirtRegI->end <= LiveUnionI.start() && "Expected non-overlap");
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// Advance the iterator that ends first.
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VirtRegI = VirtReg->advanceTo(VirtRegI, LiveUnionI.start());
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if (VirtRegI == VirtRegEnd)
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break;
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// Detect overlap, handle above.
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if (VirtRegI->start < LiveUnionI.stop())
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continue;
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// Still not overlapping. Catch up LiveUnionI.
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LiveUnionI.advanceTo(VirtRegI->start);
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}
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SeenAllInterferences = true;
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return InterferingVRegs.size();
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}
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bool LiveIntervalUnion::Query::checkLoopInterference(MachineLoopRange *Loop) {
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// VirtReg is likely live throughout the loop, so start by checking LIU-Loop
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// overlaps.
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IntervalMapOverlaps<LiveIntervalUnion::Map, MachineLoopRange::Map>
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Overlaps(LiveUnion->getMap(), Loop->getMap());
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if (!Overlaps.valid())
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return false;
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// The loop is overlapping an LIU assignment. Check VirtReg as well.
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LiveInterval::iterator VRI = VirtReg->find(Overlaps.start());
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for (;;) {
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if (VRI == VirtReg->end())
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return false;
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if (VRI->start < Overlaps.stop())
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return true;
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Overlaps.advanceTo(VRI->start);
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if (!Overlaps.valid())
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return false;
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if (Overlaps.start() < VRI->end)
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return true;
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VRI = VirtReg->advanceTo(VRI, Overlaps.start());
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}
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}
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