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https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
288 lines
14 KiB
LLVM
288 lines
14 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare { float, i1 } @llvm.AMDGPU.div.scale.f32(float, float, i1) nounwind readnone
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declare { double, i1 } @llvm.AMDGPU.div.scale.f64(double, double, i1) nounwind readnone
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; SI-LABEL @test_div_scale_f32_1:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_2:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f64_1:
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
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%a = load double addrspace(1)* %gep.0, align 8
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%b = load double addrspace(1)* %gep.1, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_1:
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
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%a = load double addrspace(1)* %gep.0, align 8
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%b = load double addrspace(1)* %gep.1, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_num_1:
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
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; SI-DAG: s_load_dword [[A:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%b = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_num_2:
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
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; SI-DAG: s_load_dword [[A:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%b = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_den_1:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
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; SI-DAG: s_load_dword [[B:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%a = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_den_2:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
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; SI-DAG: s_load_dword [[B:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%a = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_num_1:
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
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; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%b = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_num_2:
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; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%b = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_den_1:
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
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; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%a = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_den_2:
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
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; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%a = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f32_all_scalar_1:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, float %b) nounwind {
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_all_scalar_2:
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, float %b) nounwind {
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f64_all_scalar_1:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]]
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; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]]
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}}
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double %a, double %b) nounwind {
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_all_scalar_2:
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; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
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; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]]
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %a, double %b) nounwind {
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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