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Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
InstrSched | ||
InstrSelection | ||
Mapping | ||
ModuloScheduling | ||
PostOpts | ||
PreOpts | ||
RegAlloc | ||
LiveVariables.cpp | ||
MachineCodeEmitter.cpp | ||
MachineCodeForInstruction.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
MachineInstrAnnot.cpp | ||
Makefile | ||
PHIElimination.cpp | ||
PrologEpilogInserter.cpp | ||
RegAllocLocal.cpp | ||
RegAllocSimple.cpp |