llvm-6502/lib/Target
Misha Brukman 6ddd9d87a7 One of the first major changes to make the work of JITting easier: adding
annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.

This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.

As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 22:32:38 +00:00
..
CBackend Add support for setjmp/longjmp primitives 2003-05-17 22:26:33 +00:00
SparcV9 One of the first major changes to make the work of JITting easier: adding 2003-05-27 22:32:38 +00:00
X86 Renamed opIsDef to opIsDefOnly. 2003-05-27 00:03:17 +00:00
Makefile X86 target builds fine now 2002-11-20 20:17:03 +00:00
MRegisterInfo.cpp Capture more information in ctor 2002-12-28 20:34:18 +00:00
TargetData.cpp * Fix divide by zero error with empty structs 2003-05-21 18:08:44 +00:00
TargetInstrInfo.cpp Rename MachineInstrInfo -> TargetInstrInfo 2003-01-14 22:00:31 +00:00
TargetMachine.cpp The promotion rules are the same for all targets, they are set by the C standard. 2003-04-26 19:47:36 +00:00
TargetSchedInfo.cpp More renamings of Target/Machine*Info to Target/Target*Info 2002-12-29 03:13:05 +00:00