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annotations on instructions to specify which format they are (i.e., do they take 2 registers and 1 immediate or just 3 registers) as that changes their binary representation and hence, code emission. This makes instructions more like how X86 defines them to be. Now, writers of instruction selection must choose the correct opcode based on what instruction type they are building, which they already know. Thus, the JIT doesn't have to do the same work by `discovering' which operands an instruction really has. As this involves lots of small changes to a lot of files in lib/target/Sparc, I'll commit them individually because otherwise the diffs will be unreadable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
CBackend | ||
SparcV9 | ||
X86 | ||
Makefile | ||
MRegisterInfo.cpp | ||
TargetData.cpp | ||
TargetInstrInfo.cpp | ||
TargetMachine.cpp | ||
TargetSchedInfo.cpp |