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https://github.com/c64scene-ar/llvm-6502.git
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2f435511e9
if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
574 lines
22 KiB
TableGen
574 lines
22 KiB
TableGen
//===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// X86 Instruction Format Definitions.
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//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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class Format<bits<6> val> {
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bits<6> Value = val;
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}
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def Pseudo : Format<0>; def RawFrm : Format<1>;
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def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
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def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
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def MRMSrcMem : Format<6>;
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def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
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def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
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def MRM6r : Format<22>; def MRM7r : Format<23>;
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def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
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def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
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def MRM6m : Format<30>; def MRM7m : Format<31>;
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def MRMInitReg : Format<32>;
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def MRM_C1 : Format<33>;
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def MRM_C2 : Format<34>;
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def MRM_C3 : Format<35>;
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def MRM_C4 : Format<36>;
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def MRM_C8 : Format<37>;
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def MRM_C9 : Format<38>;
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def MRM_E8 : Format<39>;
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def MRM_F0 : Format<40>;
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def MRM_F8 : Format<41>;
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def MRM_F9 : Format<42>;
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def RawFrmImm8 : Format<43>;
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def RawFrmImm16 : Format<44>;
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def MRM_D0 : Format<45>;
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def MRM_D1 : Format<46>;
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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// machine code emitter.
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class ImmType<bits<3> val> {
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bits<3> Value = val;
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}
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def NoImm : ImmType<0>;
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def Imm8 : ImmType<1>;
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def Imm8PCRel : ImmType<2>;
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def Imm16 : ImmType<3>;
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def Imm16PCRel : ImmType<4>;
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def Imm32 : ImmType<5>;
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def Imm32PCRel : ImmType<6>;
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def Imm64 : ImmType<7>;
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// FPFormat - This specifies what form this FP instruction has. This is used by
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// the Floating-Point stackifier pass.
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class FPFormat<bits<3> val> {
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bits<3> Value = val;
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}
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def NotFP : FPFormat<0>;
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def ZeroArgFP : FPFormat<1>;
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def OneArgFP : FPFormat<2>;
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def OneArgFPRW : FPFormat<3>;
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def TwoArgFP : FPFormat<4>;
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def CompareFP : FPFormat<5>;
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def CondMovFP : FPFormat<6>;
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def SpecialFP : FPFormat<7>;
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// Class specifying the SSE execution domain, used by the SSEDomainFix pass.
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// Keep in sync with tables in X86InstrInfo.cpp.
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class Domain<bits<2> val> {
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bits<2> Value = val;
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}
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def GenericDomain : Domain<0>;
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def SSEPackedSingle : Domain<1>;
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def SSEPackedDouble : Domain<2>;
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def SSEPackedInt : Domain<3>;
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// Prefix byte classes which are used to indicate to the ad-hoc machine code
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// emitter that various prefix bytes are required.
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class OpSize { bit hasOpSizePrefix = 1; }
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class AdSize { bit hasAdSizePrefix = 1; }
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class REX_W { bit hasREX_WPrefix = 1; }
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class LOCK { bit hasLockPrefix = 1; }
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class SegFS { bits<2> SegOvrBits = 1; }
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class SegGS { bits<2> SegOvrBits = 2; }
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class TB { bits<5> Prefix = 1; }
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class REP { bits<5> Prefix = 2; }
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class D8 { bits<5> Prefix = 3; }
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class D9 { bits<5> Prefix = 4; }
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class DA { bits<5> Prefix = 5; }
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class DB { bits<5> Prefix = 6; }
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class DC { bits<5> Prefix = 7; }
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class DD { bits<5> Prefix = 8; }
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class DE { bits<5> Prefix = 9; }
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class DF { bits<5> Prefix = 10; }
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class XD { bits<5> Prefix = 11; }
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class XS { bits<5> Prefix = 12; }
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class T8 { bits<5> Prefix = 13; }
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class TA { bits<5> Prefix = 14; }
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class A6 { bits<5> Prefix = 15; }
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class A7 { bits<5> Prefix = 16; }
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class T8XD { bits<5> Prefix = 17; }
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class T8XS { bits<5> Prefix = 18; }
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class TAXD { bits<5> Prefix = 19; }
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class VEX { bit hasVEXPrefix = 1; }
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class VEX_W { bit hasVEX_WPrefix = 1; }
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class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
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class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
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class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
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class VEX_L { bit hasVEX_L = 1; }
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class VEX_LIG { bit ignoresVEX_L = 1; }
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class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
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class XOP_W { bit hasXOP_WPrefix = 1; }
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class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
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string AsmStr, Domain d = GenericDomain>
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: Instruction {
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let Namespace = "X86";
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bits<8> Opcode = opcod;
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Format Form = f;
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bits<6> FormBits = Form.Value;
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ImmType ImmT = i;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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string AsmString = AsmStr;
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// If this is a pseudo instruction, mark it isCodeGenOnly.
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let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
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//
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// Attributes specific to X86 instructions...
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//
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
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bits<5> Prefix = 0; // Which prefix byte does this inst have?
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bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
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FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
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bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
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bits<2> SegOvrBits = 0; // Segment override prefix.
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Domain ExeDomain = d;
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bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
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bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
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bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
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bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
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// encode the third operand?
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bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
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// to be encoded in a immediate field?
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bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
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bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
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bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
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bit hasXOP_WPrefix = 0; // Same bit as VEX_W, but used for swapping operands
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// TSFlags layout should be kept in sync with X86InstrInfo.h.
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let TSFlags{5-0} = FormBits;
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let TSFlags{6} = hasOpSizePrefix;
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let TSFlags{7} = hasAdSizePrefix;
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let TSFlags{12-8} = Prefix;
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let TSFlags{13} = hasREX_WPrefix;
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let TSFlags{16-14} = ImmT.Value;
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let TSFlags{19-17} = FPForm.Value;
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let TSFlags{20} = hasLockPrefix;
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let TSFlags{22-21} = SegOvrBits;
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let TSFlags{24-23} = ExeDomain.Value;
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let TSFlags{32-25} = Opcode;
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let TSFlags{33} = hasVEXPrefix;
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let TSFlags{34} = hasVEX_WPrefix;
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let TSFlags{35} = hasVEX_4VPrefix;
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let TSFlags{36} = hasVEX_4VOp3Prefix;
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let TSFlags{37} = hasVEX_i8ImmReg;
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let TSFlags{38} = hasVEX_L;
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let TSFlags{39} = ignoresVEX_L;
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let TSFlags{40} = has3DNow0F0FOpcode;
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let TSFlags{41} = hasXOP_WPrefix;
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}
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class PseudoI<dag oops, dag iops, list<dag> pattern>
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: X86Inst<0, Pseudo, NoImm, oops, iops, ""> {
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let Pattern = pattern;
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}
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class I<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d = GenericDomain>
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: X86Inst<o, f, NoImm, outs, ins, asm, d> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d = GenericDomain>
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: X86Inst<o, f, Imm8, outs, ins, asm, d> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm16, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm32, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern>
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: X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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// FPStack Instruction Templates:
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
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: I<o, F, outs, ins, asm, []> {}
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// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
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: X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
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let FPForm = fp;
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let Pattern = pattern;
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}
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// Templates for instructions that use a 16- or 32-bit segmented address as
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// their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
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//
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// Iseg16 - 16-bit segment selector, 16-bit offset
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// Iseg32 - 16-bit segment selector, 32-bit offset
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class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern> : X86Inst<o, f, Imm16, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern> : X86Inst<o, f, Imm32, outs, ins, asm> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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// SI - SSE 1 & 2 scalar instructions
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class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern> {
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let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
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!if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
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// AVX instructions have a 'v' prefix in the mnemonic
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let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
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}
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// SIi8 - SSE 1 & 2 scalar instructions
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class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern> {
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let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
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!if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
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// AVX instructions have a 'v' prefix in the mnemonic
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let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
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}
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// PI - SSE 1 & 2 packed instructions
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class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
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Domain d>
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: I<o, F, outs, ins, asm, pattern, d> {
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let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
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!if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
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// AVX instructions have a 'v' prefix in the mnemonic
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let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
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}
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// PIi8 - SSE 1 & 2 packed instructions with immediate
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class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, Domain d>
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: Ii8<o, F, outs, ins, asm, pattern, d> {
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let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
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!if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
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// AVX instructions have a 'v' prefix in the mnemonic
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let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
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}
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// SSE1 Instruction Templates:
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//
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// SSI - SSE1 instructions with XS prefix.
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// PSI - SSE1 instructions with TB prefix.
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// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
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// VSSI - SSE1 instructions with XS prefix in AVX form.
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// VPSI - SSE1 instructions with TB prefix in AVX form.
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class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
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class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
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class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
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Requires<[HasSSE1]>;
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class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
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Requires<[HasSSE1]>;
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class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
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Requires<[HasAVX]>;
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class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
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Requires<[HasAVX]>;
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class VoPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
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Requires<[HasSSE1orAVX]>;
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// SSE2 Instruction Templates:
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//
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// SDI - SSE2 instructions with XD prefix.
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// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
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// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
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// PDI - SSE2 instructions with TB and OpSize prefixes.
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// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
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// VSDI - SSE2 instructions with XD prefix in AVX form.
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// VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
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class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
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class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
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class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
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class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
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Requires<[HasSSE2]>;
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class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
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Requires<[HasSSE2]>;
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class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
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Requires<[HasAVX]>;
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class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>, TB,
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OpSize, Requires<[HasAVX]>;
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// SSE3 Instruction Templates:
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//
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// S3I - SSE3 instructions with TB and OpSize prefixes.
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// S3SI - SSE3 instructions with XS prefix.
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// S3DI - SSE3 instructions with XD prefix.
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class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
|
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Requires<[HasSSE3]>;
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class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
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|
Requires<[HasSSE3]>;
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|
class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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|
: I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
|
|
Requires<[HasSSE3]>;
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|
|
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// SSSE3 Instruction Templates:
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//
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// SS38I - SSSE3 instructions with T8 prefix.
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// SS3AI - SSSE3 instructions with TA prefix.
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|
//
|
|
// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
|
|
// uses the MMX registers. We put those instructions here because they better
|
|
// fit into the SSSE3 instruction category rather than the MMX category.
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|
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class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
|
|
Requires<[HasSSSE3]>;
|
|
class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
Requires<[HasSSSE3]>;
|
|
|
|
// SSE4.1 Instruction Templates:
|
|
//
|
|
// SS48I - SSE 4.1 instructions with T8 prefix.
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|
// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
|
|
//
|
|
class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
|
|
Requires<[HasSSE41]>;
|
|
class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
Requires<[HasSSE41]>;
|
|
|
|
// SSE4.2 Instruction Templates:
|
|
//
|
|
// SS428I - SSE 4.2 instructions with T8 prefix.
|
|
class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
|
|
Requires<[HasSSE42]>;
|
|
|
|
// SS42FI - SSE 4.2 instructions with T8XD prefix.
|
|
class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>;
|
|
|
|
// SS42AI = SSE 4.2 instructions with TA prefix
|
|
class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
Requires<[HasSSE42]>;
|
|
|
|
// AVX Instruction Templates:
|
|
// Instructions introduced in AVX (no SSE equivalent forms)
|
|
//
|
|
// AVX8I - AVX instructions with T8 and OpSize prefix.
|
|
// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
|
|
class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
|
|
Requires<[HasAVX]>;
|
|
class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
|
|
Requires<[HasAVX]>;
|
|
|
|
// AVX2 Instruction Templates:
|
|
// Instructions introduced in AVX2 (no SSE equivalent forms)
|
|
//
|
|
// AVX28I - AVX2 instructions with T8 and OpSize prefix.
|
|
// AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
|
|
class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
|
|
Requires<[HasAVX2]>;
|
|
class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
|
|
Requires<[HasAVX2]>;
|
|
|
|
// AES Instruction Templates:
|
|
//
|
|
// AES8I
|
|
// These use the same encoding as the SSE4.2 T8 and TA encodings.
|
|
class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag>pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
|
|
Requires<[HasAES]>;
|
|
|
|
class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
Requires<[HasAES]>;
|
|
|
|
// CLMUL Instruction Templates
|
|
class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag>pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
OpSize, Requires<[HasCLMUL]>;
|
|
|
|
class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag>pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
|
|
|
|
// FMA3 Instruction Templates
|
|
class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag>pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
|
|
OpSize, VEX_4V, Requires<[HasFMA3]>;
|
|
|
|
// FMA4 Instruction Templates
|
|
class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag>pattern>
|
|
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
|
|
OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
|
|
|
|
// X86-64 Instruction templates...
|
|
//
|
|
|
|
class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern>, REX_W;
|
|
class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern>, REX_W;
|
|
class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii32<o, F, outs, ins, asm, pattern>, REX_W;
|
|
|
|
class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
|
|
let Pattern = pattern;
|
|
let CodeSize = 3;
|
|
}
|
|
|
|
class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: SSI<o, F, outs, ins, asm, pattern>, REX_W;
|
|
class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: SDI<o, F, outs, ins, asm, pattern>, REX_W;
|
|
class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: PDI<o, F, outs, ins, asm, pattern>, REX_W;
|
|
class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: VPDI<o, F, outs, ins, asm, pattern>, VEX_W;
|
|
|
|
// MMX Instruction templates
|
|
//
|
|
|
|
// MMXI - MMX instructions with TB prefix.
|
|
// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
|
|
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
|
|
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
|
|
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
|
|
// MMXID - MMX instructions with XD prefix.
|
|
// MMXIS - MMX instructions with XS prefix.
|
|
class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
|
|
class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
|
|
class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
|
|
class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
|
|
class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
|
|
class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
|
|
class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
|
|
list<dag> pattern>
|
|
: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
|