mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2f68b311a1
This patch provides initial implementation of load address
macro instruction for Mips. We have implemented two kinds
of expansions with their variations depending on the size
of immediate operand:
1) load address with immediate value directly:
* la d,j => addiu d,$zero,j (for -32768 <= j <= 65535)
* la d,j => lui d,hi16(j)
ori d,d,lo16(j) (for any other 32 bit value of j)
2) load load address with register offset value
* la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535)
* la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j)
ori d,d,lo16(j)
addu d,d,s
This patch does not cover the case when the address is loaded
from the value of the label or function.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
1273 lines
50 KiB
TableGen
1273 lines
50 KiB
TableGen
//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mips profiles and nodes
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//===----------------------------------------------------------------------===//
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def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<3, 4>,
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SDTCisInt<4>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
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[SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisSameAs<2, 3>]>;
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def SDT_MipsDivRem : SDTypeProfile<0, 2,
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[SDTCisInt<0>,
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SDTCisSameAs<0, 1>]>;
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
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SDTCisSameAs<0, 1>]>;
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def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
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def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
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SDTCisSameAs<0, 4>]>;
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def SDTMipsLoadLR : SDTypeProfile<1, 2,
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[SDTCisInt<0>, SDTCisPtrTy<1>,
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SDTCisSameAs<0, 2>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
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[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
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SDNPVariadic]>;
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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// TlsGd node is used to handle General Dynamic TLS
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def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
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// TprelHi and TprelLo nodes are used to handle Local Exec TLS
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def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
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def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
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// Thread pointer
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def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
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// Return
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def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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[SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPSideEffect,
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SDNPOptInGlue, SDNPOutGlue]>;
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// MAdd*/MSub* nodes
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def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
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[SDNPOptInGlue, SDNPOutGlue]>;
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// DivRem(u) nodes
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def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
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[SDNPOutGlue]>;
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// Target constant nodes that are not part of any isel patterns and remain
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// unchanged can cause instructions with illegal operands to be emitted.
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// Wrapper node patterns give the instruction selector a chance to replace
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// target constant nodes that would otherwise remain unchanged with ADDiu
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// nodes. Without these wrapper node patterns, the following conditional move
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// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
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// compiled:
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// movn %got(d)($gp), %got(c)($gp), $4
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// This instruction is illegal since movn can take only register operands.
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def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
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// Pointer to dynamically allocated stack area.
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def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
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[SDNPHasChain, SDNPInGlue]>;
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def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
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def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
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def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
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def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
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AssemblerPredicate<"FeatureSEInReg">;
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def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
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AssemblerPredicate<"FeatureBitCount">;
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def HasSwap : Predicate<"Subtarget.hasSwap()">,
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AssemblerPredicate<"FeatureSwap">;
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def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
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AssemblerPredicate<"FeatureCondMov">;
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def HasMips32 : Predicate<"Subtarget.hasMips32()">,
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AssemblerPredicate<"FeatureMips32">;
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def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
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AssemblerPredicate<"FeatureMips32r2">;
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def HasMips64 : Predicate<"Subtarget.hasMips64()">,
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AssemblerPredicate<"FeatureMips64">;
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def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
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AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
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def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
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AssemblerPredicate<"!FeatureMips64">;
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def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
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AssemblerPredicate<"FeatureMips64r2">;
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def IsN64 : Predicate<"Subtarget.isABI_N64()">,
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AssemblerPredicate<"FeatureN64">;
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def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
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AssemblerPredicate<"!FeatureN64">;
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def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
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AssemblerPredicate<"FeatureMips16">;
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def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
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AssemblerPredicate<"FeatureMips32">;
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def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
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AssemblerPredicate<"FeatureMips32">;
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def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
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AssemblerPredicate<"FeatureMips32">;
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def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
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AssemblerPredicate<"!FeatureMips16">;
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class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
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let Predicates = [HasStandardEncoding];
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}
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "MipsInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def jmptarget : Operand<OtherVT> {
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let EncoderMethod = "getJumpTargetOpValue";
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}
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def brtarget : Operand<OtherVT> {
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let EncoderMethod = "getBranchTargetOpValue";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget";
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}
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def calltarget : Operand<iPTR> {
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let EncoderMethod = "getJumpTargetOpValue";
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}
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def calltarget64: Operand<i64>;
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def simm16 : Operand<i32> {
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let DecoderMethod= "DecodeSimm16";
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}
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def simm16_64 : Operand<i64>;
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def shamt : Operand<i32>;
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// Unsigned Operand
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def uimm16 : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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}
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def MipsMemAsmOperand : AsmOperandClass {
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let Name = "Mem";
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let ParserMethod = "parseMemOperand";
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}
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// Address operand
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def mem : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPURegs, simm16);
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let EncoderMethod = "getMemEncoding";
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let ParserMatchClass = MipsMemAsmOperand;
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}
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def mem64 : Operand<i64> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU64Regs, simm16_64);
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let EncoderMethod = "getMemEncoding";
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let ParserMatchClass = MipsMemAsmOperand;
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}
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def mem_ea : Operand<i32> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops CPURegs, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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def mem_ea_64 : Operand<i64> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops CPU64Regs, simm16_64);
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let EncoderMethod = "getMemEncoding";
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}
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// size operand of ext instruction
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def size_ext : Operand<i32> {
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let EncoderMethod = "getSizeExtEncoding";
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let DecoderMethod = "DecodeExtSize";
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}
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// size operand of ins instruction
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def size_ins : Operand<i32> {
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let EncoderMethod = "getSizeInsEncoding";
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let DecoderMethod = "DecodeInsSize";
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}
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// Transformation Function - get the lower 16 bits.
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def LO16 : SDNodeXForm<imm, [{
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return getImm(N, N->getZExtValue() & 0xFFFF);
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}]>;
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// Transformation Function - get the higher 16 bits.
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def HI16 : SDNodeXForm<imm, [{
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return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
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}]>;
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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// immediate are caught.
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// e.g. addiu, sltiu
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def immZExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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else
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return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
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}], LO16>;
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// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
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def immLow16Zero : PatLeaf<(imm), [{
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int64_t Val = N->getSExtValue();
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return isInt<32>(Val) && !(Val & 0xffff);
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}]>;
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// shamt field must fit in 5 bits.
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def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr :
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ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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/// Move Control Registers From/To CPU Registers
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def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
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(ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
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def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
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def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
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(ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
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def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
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(ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
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def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
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(ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
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// Arithmetic and logical instructions with 3 register operands.
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class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
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let shamt = 0;
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let isCommutable = isComm;
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let isReMaterializable = 1;
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}
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
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InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
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let shamt = 0;
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let isCommutable = isComm;
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}
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// Arithmetic and logical instructions with 2 register operands.
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class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type, RegisterClass RC> :
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FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
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[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
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let isReMaterializable = 1;
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}
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type, RegisterClass RC> :
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FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
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!strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
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class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
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FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
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let rd = 0;
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let shamt = 0;
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let isCommutable = isComm;
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}
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// Logical
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
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FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rs, $rt"),
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[(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
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let shamt = 0;
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let isCommutable = 1;
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}
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// Shifts
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class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode, PatFrag PF, Operand ImmOpnd,
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RegisterClass RC>:
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FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
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!strconcat(instr_asm, "\t$rd, $rt, $shamt"),
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[(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
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let rs = isRotate;
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}
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// 32-bit shift instructions.
|
|
class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
|
|
SDNode OpNode>:
|
|
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
|
|
|
|
class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
|
|
SDNode OpNode, RegisterClass RC>:
|
|
FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rt, $rs"),
|
|
[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
|
|
let shamt = isRotate;
|
|
}
|
|
|
|
// Load Upper Imediate
|
|
class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
|
|
FI<op, (outs RC:$rt), (ins Imm:$imm16),
|
|
!strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
|
|
let rs = 0;
|
|
let neverHasSideEffects = 1;
|
|
let isReMaterializable = 1;
|
|
}
|
|
|
|
class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
|
|
InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
|
|
bits<21> addr;
|
|
let Inst{25-21} = addr{20-16};
|
|
let Inst{15-0} = addr{15-0};
|
|
let DecoderMethod = "DecodeMem";
|
|
}
|
|
|
|
// Memory Load/Store
|
|
let canFoldAsLoad = 1 in
|
|
class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
|
|
Operand MemOpnd, bit Pseudo>:
|
|
FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
|
|
!strconcat(instr_asm, "\t$rt, $addr"),
|
|
[(set RC:$rt, (OpNode addr:$addr))], IILoad> {
|
|
let isPseudo = Pseudo;
|
|
}
|
|
|
|
class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
|
|
Operand MemOpnd, bit Pseudo>:
|
|
FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
|
|
!strconcat(instr_asm, "\t$rt, $addr"),
|
|
[(OpNode RC:$rt, addr:$addr)], IIStore> {
|
|
let isPseudo = Pseudo;
|
|
}
|
|
|
|
// 32-bit load.
|
|
multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// 64-bit load.
|
|
multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// 32-bit store.
|
|
multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// 64-bit store.
|
|
multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
|
bit Pseudo = 0> {
|
|
def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// Load/Store Left/Right
|
|
let canFoldAsLoad = 1 in
|
|
class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
|
|
RegisterClass RC, Operand MemOpnd> :
|
|
FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
|
|
!strconcat(instr_asm, "\t$rt, $addr"),
|
|
[(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
|
|
string Constraints = "$src = $rt";
|
|
}
|
|
|
|
class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
|
|
RegisterClass RC, Operand MemOpnd>:
|
|
FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
|
|
!strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
|
|
IIStore>;
|
|
|
|
// 32-bit load left/right.
|
|
multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
|
|
def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// 64-bit load left/right.
|
|
multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
|
|
def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// 32-bit store left/right.
|
|
multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
|
|
def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// 64-bit store left/right.
|
|
multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
|
|
def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
}
|
|
|
|
// Conditional Branch
|
|
class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
|
|
BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
|
|
!strconcat(instr_asm, "\t$rs, $rt, $imm16"),
|
|
[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let hasDelaySlot = 1;
|
|
let Defs = [AT];
|
|
}
|
|
|
|
class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
|
|
RegisterClass RC>:
|
|
BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
|
|
!strconcat(instr_asm, "\t$rs, $imm16"),
|
|
[(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
|
|
let rt = _rt;
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let hasDelaySlot = 1;
|
|
let Defs = [AT];
|
|
}
|
|
|
|
// SetCC
|
|
class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
|
|
RegisterClass RC>:
|
|
FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rs, $rt"),
|
|
[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
|
|
IIAlu> {
|
|
let shamt = 0;
|
|
}
|
|
|
|
class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
|
|
PatLeaf imm_type, RegisterClass RC>:
|
|
FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
|
|
!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
|
|
[(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
|
|
IIAlu>;
|
|
|
|
// Jump
|
|
class JumpFJ<bits<6> op, string instr_asm>:
|
|
FJ<op, (outs), (ins jmptarget:$target),
|
|
!strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
|
|
let isBranch=1;
|
|
let isTerminator=1;
|
|
let isBarrier=1;
|
|
let hasDelaySlot = 1;
|
|
let Predicates = [RelocStatic, HasStandardEncoding];
|
|
let DecoderMethod = "DecodeJumpTarget";
|
|
let Defs = [AT];
|
|
}
|
|
|
|
// Unconditional branch
|
|
class UncondBranch<bits<6> op, string instr_asm>:
|
|
BranchBase<op, (outs), (ins brtarget:$imm16),
|
|
!strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
|
|
let rs = 0;
|
|
let rt = 0;
|
|
let isBranch = 1;
|
|
let isTerminator = 1;
|
|
let isBarrier = 1;
|
|
let hasDelaySlot = 1;
|
|
let Predicates = [RelocPIC, HasStandardEncoding];
|
|
let Defs = [AT];
|
|
}
|
|
|
|
// Base class for indirect branch and return instruction classes.
|
|
let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
|
|
class JumpFR<RegisterClass RC, list<dag> pattern>:
|
|
FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> {
|
|
let rt = 0;
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
}
|
|
|
|
// Indirect branch
|
|
class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> {
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
}
|
|
|
|
// Return instruction
|
|
class RetBase<RegisterClass RC>: JumpFR<RC, []> {
|
|
let isReturn = 1;
|
|
let isCodeGenOnly = 1;
|
|
let hasCtrlDep = 1;
|
|
let hasExtraSrcRegAllocReq = 1;
|
|
}
|
|
|
|
// Jump and Link (Call)
|
|
let isCall=1, hasDelaySlot=1, Defs = [RA] in {
|
|
class JumpLink<bits<6> op, string instr_asm>:
|
|
FJ<op, (outs), (ins calltarget:$target),
|
|
!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
|
|
IIBranch> {
|
|
let DecoderMethod = "DecodeJumpTarget";
|
|
}
|
|
|
|
class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
|
|
RegisterClass RC>:
|
|
FR<op, func, (outs), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
|
|
let rt = 0;
|
|
let rd = 31;
|
|
let shamt = 0;
|
|
}
|
|
|
|
class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
|
|
FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
|
|
!strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
|
|
let rt = _rt;
|
|
}
|
|
}
|
|
|
|
// Mul, Div
|
|
class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
|
|
RegisterClass RC, list<Register> DefRegs>:
|
|
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
let isCommutable = 1;
|
|
let Defs = DefRegs;
|
|
let neverHasSideEffects = 1;
|
|
}
|
|
|
|
class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
|
|
Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
|
|
|
|
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
|
|
RegisterClass RC, list<Register> DefRegs>:
|
|
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
|
|
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
|
|
[(op RC:$rs, RC:$rt)], itin> {
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
let Defs = DefRegs;
|
|
}
|
|
|
|
class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
|
|
Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
|
|
|
|
// Move from Hi/Lo
|
|
class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
|
|
list<Register> UseRegs>:
|
|
FR<0x00, func, (outs RC:$rd), (ins),
|
|
!strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
|
|
let rs = 0;
|
|
let rt = 0;
|
|
let shamt = 0;
|
|
let Uses = UseRegs;
|
|
let neverHasSideEffects = 1;
|
|
}
|
|
|
|
class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
|
|
list<Register> DefRegs>:
|
|
FR<0x00, func, (outs), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
|
|
let rt = 0;
|
|
let rd = 0;
|
|
let shamt = 0;
|
|
let Defs = DefRegs;
|
|
let neverHasSideEffects = 1;
|
|
}
|
|
|
|
class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
|
|
FMem<opc, (outs RC:$rt), (ins Mem:$addr),
|
|
instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
// Count Leading Ones/Zeros in Word
|
|
class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
|
|
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rd, $rs"),
|
|
[(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
|
|
Requires<[HasBitCount, HasStandardEncoding]> {
|
|
let shamt = 0;
|
|
let rt = rd;
|
|
}
|
|
|
|
class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
|
|
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
|
|
!strconcat(instr_asm, "\t$rd, $rs"),
|
|
[(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
|
|
Requires<[HasBitCount, HasStandardEncoding]> {
|
|
let shamt = 0;
|
|
let rt = rd;
|
|
}
|
|
|
|
// Sign Extend in Register.
|
|
class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
|
|
RegisterClass RC>:
|
|
FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rt"),
|
|
[(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
|
|
let rs = 0;
|
|
let shamt = sa;
|
|
let Predicates = [HasSEInReg, HasStandardEncoding];
|
|
}
|
|
|
|
// Subword Swap
|
|
class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
|
|
FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
|
|
!strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
|
|
let rs = 0;
|
|
let shamt = sa;
|
|
let Predicates = [HasSwap, HasStandardEncoding];
|
|
let neverHasSideEffects = 1;
|
|
}
|
|
|
|
// Read Hardware
|
|
class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
|
|
: FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
|
|
"rdhwr\t$rt, $rd", [], IIAlu> {
|
|
let rs = 0;
|
|
let shamt = 0;
|
|
}
|
|
|
|
// Ext and Ins
|
|
class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
|
FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
|
|
!strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
|
|
[(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
|
|
bits<5> pos;
|
|
bits<5> sz;
|
|
let rd = sz;
|
|
let shamt = pos;
|
|
let Predicates = [HasMips32r2, HasStandardEncoding];
|
|
}
|
|
|
|
class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
|
FR<0x1f, _funct, (outs RC:$rt),
|
|
(ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
|
|
!strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
|
|
[(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
|
|
NoItinerary> {
|
|
bits<5> pos;
|
|
bits<5> sz;
|
|
let rd = sz;
|
|
let shamt = pos;
|
|
let Predicates = [HasMips32r2, HasStandardEncoding];
|
|
let Constraints = "$src = $rt";
|
|
}
|
|
|
|
// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
|
|
class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
|
|
RegisterClass PRC> :
|
|
PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
|
|
!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
|
|
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
|
|
|
|
multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
|
|
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
}
|
|
}
|
|
|
|
// Atomic Compare & Swap.
|
|
class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
|
|
RegisterClass PRC> :
|
|
PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
|
|
!strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
|
|
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
|
|
|
|
multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
|
|
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
}
|
|
}
|
|
|
|
class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
|
|
FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
|
|
!strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
|
|
let mayLoad = 1;
|
|
}
|
|
|
|
class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
|
|
FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
|
|
!strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
|
|
let mayStore = 1;
|
|
let Constraints = "$rt = $dst";
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Pseudo instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Return RA.
|
|
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
|
|
def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>;
|
|
|
|
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
|
|
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
|
|
"!ADJCALLSTACKDOWN $amt",
|
|
[(callseq_start timm:$amt)]>;
|
|
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
|
"!ADJCALLSTACKUP $amt1",
|
|
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
|
}
|
|
|
|
// When handling PIC code the assembler needs .cpload and .cprestore
|
|
// directives. If the real instructions corresponding these directives
|
|
// are used, we have the same behavior, but get also a bunch of warnings
|
|
// from the assembler.
|
|
let neverHasSideEffects = 1 in
|
|
def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp),
|
|
".cprestore\t$loc", []>;
|
|
|
|
let usesCustomInserter = 1 in {
|
|
defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
|
|
defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
|
|
defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
|
|
defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
|
|
defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
|
|
defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
|
|
defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
|
|
defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
|
|
defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
|
|
defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
|
|
defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
|
|
defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
|
|
defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
|
|
defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
|
|
defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
|
|
defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
|
|
defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
|
|
defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
|
|
|
|
defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
|
|
defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
|
|
defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
|
|
|
|
defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
|
|
defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
|
|
defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction definition
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
|
|
MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
|
|
!strconcat(instr_asm, "\t$rt, $imm32")> ;
|
|
def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
|
|
|
|
class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
|
|
MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
|
|
!strconcat(instr_asm, "\t$rt, $addr")> ;
|
|
def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
|
|
|
|
class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
|
|
MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
|
|
!strconcat(instr_asm, "\t$rt, $imm32")> ;
|
|
def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MipsI Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Arithmetic Instructions (ALU Immediate)
|
|
def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
|
|
def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
|
|
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
|
|
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
|
|
def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
|
|
def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
|
|
def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
|
|
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
|
|
|
|
/// Arithmetic Instructions (3-Operand, R-Type)
|
|
def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
|
|
def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
|
|
def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
|
|
def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
|
|
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
|
|
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
|
|
def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
|
|
def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
|
|
def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
|
|
def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
|
|
|
|
/// Shift Instructions
|
|
def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
|
|
def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
|
|
def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
|
|
def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
|
|
def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
|
|
def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
|
|
|
|
// Rotate Instructions
|
|
let Predicates = [HasMips32r2, HasStandardEncoding] in {
|
|
def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
|
|
def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
|
|
}
|
|
|
|
/// Load and Store Instructions
|
|
/// aligned
|
|
defm LB : LoadM32<0x20, "lb", sextloadi8>;
|
|
defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
|
|
defm LH : LoadM32<0x21, "lh", sextloadi16>;
|
|
defm LHu : LoadM32<0x25, "lhu", zextloadi16>;
|
|
defm LW : LoadM32<0x23, "lw", load>;
|
|
defm SB : StoreM32<0x28, "sb", truncstorei8>;
|
|
defm SH : StoreM32<0x29, "sh", truncstorei16>;
|
|
defm SW : StoreM32<0x2b, "sw", store>;
|
|
|
|
/// load/store left/right
|
|
defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
|
|
defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
|
|
defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
|
|
defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
|
|
|
|
let hasSideEffects = 1 in
|
|
def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
|
|
[(MipsSync imm:$stype)], NoItinerary, FrmOther>
|
|
{
|
|
bits<5> stype;
|
|
let Opcode = 0;
|
|
let Inst{25-11} = 0;
|
|
let Inst{10-6} = stype;
|
|
let Inst{5-0} = 15;
|
|
}
|
|
|
|
/// Load-linked, Store-conditional
|
|
def LL : LLBase<0x30, "ll", CPURegs, mem>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
}
|
|
|
|
def SC : SCBase<0x38, "sc", CPURegs, mem>,
|
|
Requires<[NotN64, HasStandardEncoding]>;
|
|
def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
|
|
Requires<[IsN64, HasStandardEncoding]> {
|
|
let DecoderNamespace = "Mips64";
|
|
}
|
|
|
|
/// Jump and Branch Instructions
|
|
def J : JumpFJ<0x02, "j">;
|
|
def JR : IndirectBranch<CPURegs>;
|
|
def B : UncondBranch<0x04, "b">;
|
|
def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
|
|
def BNE : CBranch<0x05, "bne", setne, CPURegs>;
|
|
def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
|
|
def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
|
|
def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
|
|
def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
|
|
|
|
let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
|
|
hasDelaySlot = 1, Defs = [RA] in
|
|
def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
|
|
|
|
def JAL : JumpLink<0x03, "jal">;
|
|
def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
|
|
def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
|
|
def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
|
|
|
|
def RET : RetBase<CPURegs>;
|
|
|
|
/// Multiply and Divide Instructions.
|
|
def MULT : Mult32<0x18, "mult", IIImul>;
|
|
def MULTu : Mult32<0x19, "multu", IIImul>;
|
|
def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
|
|
def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
|
|
|
|
def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
|
|
def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
|
|
def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
|
|
def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
|
|
|
|
/// Sign Ext In Register Instructions.
|
|
def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
|
|
def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
|
|
|
|
/// Count Leading
|
|
def CLZ : CountLeading0<0x20, "clz", CPURegs>;
|
|
def CLO : CountLeading1<0x21, "clo", CPURegs>;
|
|
|
|
/// Word Swap Bytes Within Halfwords
|
|
def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
|
|
|
|
/// No operation
|
|
let addr=0 in
|
|
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
|
|
|
|
// FrameIndexes are legalized when they are operands from load/store
|
|
// instructions. The same not happens for stack address copies, so an
|
|
// add op with mem ComplexPattern is used and the stack address copy
|
|
// can be matched. It's similar to Sparc LEA_ADDRi
|
|
def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
|
|
|
|
// DynAlloc node points to dynamically allocated stack space.
|
|
// $sp is added to the list of implicitly used registers to prevent dead code
|
|
// elimination from removing instructions that modify $sp.
|
|
let Uses = [SP] in
|
|
def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
|
|
|
|
// MADD*/MSUB*
|
|
def MADD : MArithR<0, "madd", MipsMAdd, 1>;
|
|
def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
|
|
def MSUB : MArithR<4, "msub", MipsMSub>;
|
|
def MSUBU : MArithR<5, "msubu", MipsMSubu>;
|
|
|
|
// MUL is a assembly macro in the current used ISAs. In recent ISA's
|
|
// it is a real instruction.
|
|
def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
|
|
Requires<[HasMips32, HasStandardEncoding]>;
|
|
|
|
def RDHWR : ReadHardware<CPURegs, HWRegs>;
|
|
|
|
def EXT : ExtBase<0, "ext", CPURegs>;
|
|
def INS : InsBase<4, "ins", CPURegs>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction aliases
|
|
//===----------------------------------------------------------------------===//
|
|
def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
|
|
def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
|
|
def : InstAlias<"addu $rs,$rt,$imm",
|
|
(ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
|
|
def : InstAlias<"add $rs,$rt,$imm",
|
|
(ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
|
|
def : InstAlias<"and $rs,$rt,$imm",
|
|
(ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
|
|
def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
|
|
def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
|
|
def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
|
|
def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
|
|
def : InstAlias<"slt $rs,$rt,$imm",
|
|
(SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
|
|
def : InstAlias<"xor $rs,$rt,$imm",
|
|
(XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Small immediates
|
|
def : MipsPat<(i32 immSExt16:$in),
|
|
(ADDiu ZERO, imm:$in)>;
|
|
def : MipsPat<(i32 immZExt16:$in),
|
|
(ORi ZERO, imm:$in)>;
|
|
def : MipsPat<(i32 immLow16Zero:$in),
|
|
(LUi (HI16 imm:$in))>;
|
|
|
|
// Arbitrary immediates
|
|
def : MipsPat<(i32 imm:$imm),
|
|
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
|
|
|
// Carry MipsPatterns
|
|
def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
|
|
(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
|
|
(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
|
|
(ADDiu CPURegs:$src, imm:$imm)>;
|
|
|
|
// Call
|
|
def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
|
(JAL tglobaladdr:$dst)>;
|
|
def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
|
|
(JAL texternalsym:$dst)>;
|
|
//def : MipsPat<(MipsJmpLink CPURegs:$dst),
|
|
// (JALR CPURegs:$dst)>;
|
|
|
|
// hi/lo relocs
|
|
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
|
def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
|
|
def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
|
|
def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
|
|
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
|
|
|
|
def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
|
|
def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
|
|
def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
|
|
def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
|
|
def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
|
|
|
|
def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
|
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
|
def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
|
|
(ADDiu CPURegs:$hi, tblockaddress:$lo)>;
|
|
def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
|
|
(ADDiu CPURegs:$hi, tjumptable:$lo)>;
|
|
def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
|
|
(ADDiu CPURegs:$hi, tconstpool:$lo)>;
|
|
def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
|
(ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
// gp_rel relocs
|
|
def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
|
|
(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
|
|
def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
|
|
(ADDiu CPURegs:$gp, tconstpool:$in)>;
|
|
|
|
// wrapper_pic
|
|
class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
|
|
MipsPat<(MipsWrapper RC:$gp, node:$in),
|
|
(ADDiuOp RC:$gp, node:$in)>;
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def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
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def : WrapperPat<tconstpool, ADDiu, CPURegs>;
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def : WrapperPat<texternalsym, ADDiu, CPURegs>;
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def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
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def : WrapperPat<tjumptable, ADDiu, CPURegs>;
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def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
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// Mips does not have "not", so we expand our way
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def : MipsPat<(not CPURegs:$in),
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(NOR CPURegs:$in, ZERO)>;
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// extended loads
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
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def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
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def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
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def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
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def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
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}
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// peepholes
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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}
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
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}
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// brcond patterns
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multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
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Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
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Instruction SLTiuOp, Register ZEROReg> {
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def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
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(BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
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def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
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(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
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(BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
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(BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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|
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def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
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|
(BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
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|
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def : MipsPat<(brcond RC:$cond, bb:$dst),
|
|
(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
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}
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|
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defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
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|
|
|
// setcc patterns
|
|
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
|
|
Instruction SLTuOp, Register ZEROReg> {
|
|
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
|
|
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
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def : MipsPat<(setne RC:$lhs, RC:$rhs),
|
|
(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
|
|
}
|
|
|
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multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
|
def : MipsPat<(setle RC:$lhs, RC:$rhs),
|
|
(XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
|
|
def : MipsPat<(setule RC:$lhs, RC:$rhs),
|
|
(XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
|
|
}
|
|
|
|
multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
|
def : MipsPat<(setgt RC:$lhs, RC:$rhs),
|
|
(SLTOp RC:$rhs, RC:$lhs)>;
|
|
def : MipsPat<(setugt RC:$lhs, RC:$rhs),
|
|
(SLTuOp RC:$rhs, RC:$lhs)>;
|
|
}
|
|
|
|
multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
|
|
def : MipsPat<(setge RC:$lhs, RC:$rhs),
|
|
(XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
|
|
def : MipsPat<(setuge RC:$lhs, RC:$rhs),
|
|
(XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
|
|
}
|
|
|
|
multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
|
|
Instruction SLTiuOp> {
|
|
def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
|
|
def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
|
|
}
|
|
|
|
defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
|
|
defm : SetlePats<CPURegs, SLT, SLTu>;
|
|
defm : SetgtPats<CPURegs, SLT, SLTu>;
|
|
defm : SetgePats<CPURegs, SLT, SLTu>;
|
|
defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
|
|
|
|
// select MipsDynAlloc
|
|
def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
|
|
|
|
// bswap pattern
|
|
def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "MipsInstrFPU.td"
|
|
include "Mips64InstrInfo.td"
|
|
include "MipsCondMov.td"
|
|
|
|
//
|
|
// Mips16
|
|
|
|
include "Mips16InstrFormats.td"
|
|
include "Mips16InstrInfo.td"
|
|
|
|
// DSP
|
|
include "MipsDSPInstrFormats.td"
|
|
include "MipsDSPInstrInfo.td"
|
|
|