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1c2d3c538c
For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.2 KiB
LLVM
42 lines
1.2 KiB
LLVM
; RUN: llc < %s -o /dev/null "-mtriple=thumbv7-apple-ios" -debug-only=post-RA-sched 2> %t
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; RUN: FileCheck %s < %t
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; REQUIRES: asserts
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; Make sure that mayalias store-load dependencies have one cycle
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; latency regardless of whether they are barriers or not.
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; CHECK: ** List Scheduling
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; CHECK: SU(2){{.*}}STR{{.*}}Volatile
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; CHECK-NOT: ch SU
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; CHECK: ch SU(3): Latency=1
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; CHECK-NOT: ch SU
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; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
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; CHECK-NOT: ch SU
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; CHECK: ch SU(2): Latency=1
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; CHECK-NOT: ch SU
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; CHECK: ** List Scheduling
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; CHECK: SU(2){{.*}}STR{{.*}}
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; CHECK-NOT: ch SU
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; CHECK: ch SU(3): Latency=1
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; CHECK-NOT: ch SU
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; CHECK: SU(3){{.*}}LDR{{.*}}
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; CHECK-NOT: ch SU
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; CHECK: ch SU(2): Latency=1
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; CHECK-NOT: ch SU
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define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
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entry:
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store volatile i32 65540, i32* %p1, align 4, !tbaa !0
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%0 = load volatile i32* %p2, align 4, !tbaa !0
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ret i32 %0
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}
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define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
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entry:
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store i32 65540, i32* %p1, align 4, !tbaa !0
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%0 = load i32* %p2, align 4, !tbaa !0
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ret i32 %0
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}
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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