mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 20:29:21 +00:00
d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
808 B
LLVM
26 lines
808 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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define ptx_device i32 @test_selp_i32(i1 %x, i32 %y, i32 %z) {
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; CHECK: selp.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, p{{[0-9]+}};
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%a = select i1 %x, i32 %y, i32 %z
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ret i32 %a
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}
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define ptx_device i64 @test_selp_i64(i1 %x, i64 %y, i64 %z) {
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; CHECK: selp.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}, p{{[0-9]+}};
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%a = select i1 %x, i64 %y, i64 %z
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ret i64 %a
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}
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define ptx_device float @test_selp_f32(i1 %x, float %y, float %z) {
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; CHECK: selp.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, p{{[0-9]+}};
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%a = select i1 %x, float %y, float %z
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ret float %a
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}
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define ptx_device double @test_selp_f64(i1 %x, double %y, double %z) {
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; CHECK: selp.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}, p{{[0-9]+}};
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%a = select i1 %x, double %y, double %z
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ret double %a
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}
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