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x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
150 lines
5.5 KiB
C++
150 lines
5.5 KiB
C++
//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAG class, which is used as the common
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// base class for SelectionDAG-based instruction scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAG_H
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#define LLVM_CODEGEN_SCHEDULEDAG_H
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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struct InstrStage;
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class MachineConstantPool;
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class MachineDebugInfo;
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class MachineInstr;
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class MRegisterInfo;
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class SelectionDAG;
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class SSARegMap;
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class TargetInstrInfo;
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class TargetInstrDescriptor;
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class TargetMachine;
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/// HazardRecognizer - This determines whether or not an instruction can be
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/// issued this cycle, and whether or not a noop needs to be inserted to handle
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/// the hazard.
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class HazardRecognizer {
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public:
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virtual ~HazardRecognizer();
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enum HazardType {
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NoHazard, // This instruction can be emitted at this cycle.
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Hazard, // This instruction can't be emitted at this cycle.
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NoopHazard, // This instruction can't be emitted, and needs noops.
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};
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/// getHazardType - Return the hazard type of emitting this node. There are
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/// three possible results. Either:
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/// * NoHazard: it is legal to issue this instruction on this cycle.
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/// * Hazard: issuing this instruction would stall the machine. If some
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/// other instruction is available, issue it first.
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/// * NoopHazard: issuing this instruction would break the program. If
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/// some other instruction can be issued, do so, otherwise issue a noop.
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virtual HazardType getHazardType(SDNode *Node) {
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return NoHazard;
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}
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/// EmitInstruction - This callback is invoked when an instruction is
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/// emitted, to advance the hazard state.
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virtual void EmitInstruction(SDNode *Node) {
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}
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/// AdvanceCycle - This callback is invoked when no instructions can be
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/// issued on this cycle without a hazard. This should increment the
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/// internal state of the hazard recognizer so that previously "Hazard"
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/// instructions will now not be hazards.
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virtual void AdvanceCycle() {
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}
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/// EmitNoop - This callback is invoked when a noop was added to the
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/// instruction stream.
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virtual void EmitNoop() {
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}
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};
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class ScheduleDAG {
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public:
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SelectionDAG &DAG; // DAG of the current basic block
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MachineBasicBlock *BB; // Current basic block
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const TargetMachine &TM; // Target processor
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const TargetInstrInfo *TII; // Target instruction information
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const MRegisterInfo *MRI; // Target processor register info
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SSARegMap *RegMap; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm)
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: DAG(dag), BB(bb), TM(tm) {}
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virtual ~ScheduleDAG() {}
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/// Run - perform scheduling.
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///
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MachineBasicBlock *Run();
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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return false;
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}
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/// EmitNode - Generate machine code for an node and needed dependencies.
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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///
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void EmitNode(SDNode *Node, std::map<SDNode*, unsigned> &VRBaseMap);
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/// EmitNoop - Emit a noop instruction.
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///
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void EmitNoop();
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/// Schedule - Order nodes according to selected style.
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///
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virtual void Schedule() {}
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private:
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void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
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const TargetInstrDescriptor *II,
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std::map<SDNode*, unsigned> &VRBaseMap);
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};
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ScheduleDAG *createBFS_DAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB);
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/// createSimpleDAGScheduler - This creates a simple two pass instruction
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/// scheduler.
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ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG &DAG,
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MachineBasicBlock *BB);
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/// createBURRListDAGScheduler - This creates a bottom up register usage
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/// reduction list scheduler.
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ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
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MachineBasicBlock *BB);
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/// createTDListDAGScheduler - This creates a top-down list scheduler with
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/// the specified hazard recognizer. This takes ownership of the hazard
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/// recognizer and deletes it when done.
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ScheduleDAG* createTDListDAGScheduler(SelectionDAG &DAG,
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MachineBasicBlock *BB,
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HazardRecognizer *HR);
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}
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#endif
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