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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
1.1 KiB
LLVM
29 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.AMDGPU.brev(i32) nounwind readnone
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; FUNC-LABEL: {{^}}s_brev_i32:
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; SI: s_load_dword [[VAL:s[0-9]+]],
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; SI: s_brev_b32 [[SRESULT:s[0-9]+]], [[VAL]]
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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; SI: s_endpgm
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define void @s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone
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store i32 %ctlz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_brev_i32:
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; SI: buffer_load_dword [[VAL:v[0-9]+]],
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; SI: v_bfrev_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @v_brev_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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%val = load i32, i32 addrspace(1)* %valptr, align 4
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%ctlz = call i32 @llvm.AMDGPU.brev(i32 %val) nounwind readnone
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store i32 %ctlz, i32 addrspace(1)* %out, align 4
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ret void
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}
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