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InstPrinter
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Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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2013-05-23 17:10:37 +00:00 |
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MCTargetDesc
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R600: Hide symbols of implementation details.
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2013-05-23 15:43:05 +00:00 |
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TargetInfo
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AMDGPU.h
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Revert "R600: Add a pass that merge Vector Register"
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2013-06-05 01:48:30 +00:00 |
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AMDGPU.td
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AMDGPUAsmPrinter.cpp
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Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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2013-05-23 17:10:37 +00:00 |
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
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R600/SI: Add a calling convention for compute shaders
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2013-06-03 17:40:11 +00:00 |
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AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUIndirectAddressing.cpp
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AMDGPUInstrInfo.cpp
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R600: Hide symbols of implementation details.
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2013-05-23 15:43:05 +00:00 |
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
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2013-05-22 06:36:09 +00:00 |
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AMDGPUInstructions.td
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R600/SI: Add support for global loads
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2013-06-03 17:39:43 +00:00 |
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AMDGPUIntrinsics.td
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AMDGPUISelLowering.cpp
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R600/SI: Add a calling convention for compute shaders
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2013-06-03 17:40:11 +00:00 |
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AMDGPUISelLowering.h
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R600/SI: Add support for work item and work group intrinsics
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2013-06-03 17:40:18 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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Make SubRegIndex size mandatory, following r183020.
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2013-05-31 23:45:26 +00:00 |
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AMDGPUStructurizeCFG.cpp
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Silencing an MSVC warning about mixing bool and unsigned int.
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2013-06-04 01:03:03 +00:00 |
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AMDGPUSubtarget.cpp
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Temporary fix to get rid of gcc warning.
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2013-05-29 07:32:08 +00:00 |
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AMDGPUSubtarget.h
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R600: Factorize Fetch size limit inside AMDGPUSubTarget
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2013-05-17 16:49:55 +00:00 |
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AMDGPUTargetMachine.cpp
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Revert "R600: Add a pass that merge Vector Register"
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2013-06-05 01:48:30 +00:00 |
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AMDGPUTargetMachine.h
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Fix a leak on the r600 backend.
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2013-05-23 03:31:47 +00:00 |
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AMDIL7XXDevice.cpp
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AMDIL7XXDevice.h
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AMDIL.h
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AMDILBase.td
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AMDILCFGStructurizer.cpp
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R600: Hide symbols of implementation details.
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2013-05-23 15:43:05 +00:00 |
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AMDILDevice.cpp
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AMDILDevice.h
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AMDILDeviceInfo.cpp
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AMDILDeviceInfo.h
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AMDILDevices.h
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AMDILEvergreenDevice.cpp
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AMDILEvergreenDevice.h
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.
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2013-05-22 14:57:42 +00:00 |
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelDAGToDAG.cpp
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R600: Const/Neg/Abs can be folded to dot4
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2013-06-04 23:17:15 +00:00 |
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AMDILISelLowering.cpp
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Track IR ordering of SelectionDAG nodes 2/4.
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2013-05-25 02:42:55 +00:00 |
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AMDILNIDevice.cpp
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AMDILNIDevice.h
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AMDILRegisterInfo.td
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AMDILSIDevice.cpp
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AMDILSIDevice.h
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CMakeLists.txt
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Revert "R600: Add a pass that merge Vector Register"
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2013-06-05 01:48:30 +00:00 |
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LLVMBuild.txt
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Makefile
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Processors.td
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R600ControlFlowFinalizer.cpp
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R600: CALL_FS consumes a stack size entry
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2013-06-03 15:44:42 +00:00 |
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R600Defines.h
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R600: Relax some vector constraints on Dot4.
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2013-05-17 16:50:32 +00:00 |
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R600EmitClauseMarkers.cpp
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R600: Const/Neg/Abs can be folded to dot4
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2013-06-04 23:17:15 +00:00 |
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R600ExpandSpecialInstrs.cpp
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R600: Const/Neg/Abs can be folded to dot4
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2013-06-04 23:17:15 +00:00 |
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R600InstrInfo.cpp
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R600: Make sure to schedule AR register uses and defs in the same clause
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2013-06-05 03:43:06 +00:00 |
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R600InstrInfo.h
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R600: Const/Neg/Abs can be folded to dot4
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2013-06-04 23:17:15 +00:00 |
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R600Instructions.td
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R600: Constraints input regs of interp_xy,_zw
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2013-06-03 15:44:16 +00:00 |
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R600Intrinsics.td
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R600: Improve texture handling
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2013-05-17 16:50:20 +00:00 |
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R600ISelLowering.cpp
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R600: Swizzle texture/export instructions
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2013-06-04 15:04:53 +00:00 |
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R600ISelLowering.h
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R600: Swizzle texture/export instructions
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2013-06-04 15:04:53 +00:00 |
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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2013-05-23 17:10:37 +00:00 |
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R600MachineScheduler.cpp
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R600: Make sure to schedule AR register uses and defs in the same clause
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2013-06-05 03:43:06 +00:00 |
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R600MachineScheduler.h
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R600: Make sure to schedule AR register uses and defs in the same clause
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2013-06-05 03:43:06 +00:00 |
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R600Packetizer.cpp
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R600: 3 op instructions have no write bit but the result are store in PV
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2013-06-03 15:56:12 +00:00 |
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R600RegisterInfo.cpp
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R600: Use bottom up scheduling algorithm
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2013-05-17 16:50:56 +00:00 |
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R600RegisterInfo.h
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R600: Use bottom up scheduling algorithm
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2013-05-17 16:50:56 +00:00 |
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R600RegisterInfo.td
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R600: use capital letter for PV channel
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2013-06-03 15:44:35 +00:00 |
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
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2013-05-23 17:10:37 +00:00 |
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SIAnnotateControlFlow.cpp
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SIDefines.h
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SIInsertWaits.cpp
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SIInstrFormats.td
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R600/SI: Use the same names for VOP3 operands and encoding fields
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2013-05-20 15:02:08 +00:00 |
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SIInstrInfo.cpp
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SIInstrInfo.h
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SIInstrInfo.td
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R600/SI: Add support for global loads
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2013-06-03 17:39:43 +00:00 |
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SIInstructions.td
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R600/SI: Add support for global loads
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2013-06-03 17:39:43 +00:00 |
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SIIntrinsics.td
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SIISelLowering.cpp
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R600/SI: Add support for work item and work group intrinsics
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2013-06-03 17:40:18 +00:00 |
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SIISelLowering.h
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R600/SI: Add support for work item and work group intrinsics
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2013-06-03 17:40:18 +00:00 |
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SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
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SIRegisterInfo.h
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SIRegisterInfo.td
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SISchedule.td
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