Jakob Stoklund Olesen 2da5337024 Add a TargetRegisterInfo::composeSubRegIndices hook with a default ... implementation that is correct for most targets. Tablegen will override where needed. Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing subreg indices when sustituting registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104985 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-28 18:18:53 +00:00
..
Mangler.h
SubtargetFeature.h
Target.td	Replace the SubRegSet tablegen class with a less error-prone mechanism.	2010-05-26 17:27:12 +00:00
TargetAsmBackend.h	MC: Change RelaxInstruction to only take the input and output instructions.	2010-05-26 18:15:06 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h
TargetInstrInfo.h	Implement @llvm.returnaddress. rdar://8015977.	2010-05-22 01:47:14 +00:00
TargetInstrItineraries.h
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetLoweringObjectFile.h	Add a new section and accessor for TLS data.	2010-05-22 00:00:58 +00:00
TargetMachine.h	MC: Add TargetMachine support for setting the value of MCRelaxAll with	2010-05-26 21:48:55 +00:00
TargetOpcodes.h
TargetOptions.h
TargetRegisterInfo.h	Add a TargetRegisterInfo::composeSubRegIndices hook with a default	2010-05-28 18:18:53 +00:00
TargetRegistry.h	Currently, createMachOStreamer() is invoked directly in llvm-mc which	2010-05-21 12:54:43 +00:00
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td
TargetSelectionDAGInfo.h
TargetSubtarget.h