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https://github.com/c64scene-ar/llvm-6502.git
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5e487f8dc7
This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
204 lines
4.6 KiB
LLVM
204 lines
4.6 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_v4i16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x half> %a to <4 x i16>
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ret <4 x i16> %1
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}
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define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_v2i32:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x half> %a to <2 x i32>
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ret <2 x i32> %1
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}
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define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_v1i64:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x half> %a to <1 x i64>
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ret <1 x i64> %1
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}
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define i64 @v4f16_to_i64(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_i64:
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; CHECK: fmov x0, d1
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entry:
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%1 = bitcast <4 x half> %a to i64
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ret i64 %1
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}
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define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_v2float:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x half> %a to <2 x float>
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ret <2 x float> %1
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}
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define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_v1double:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x half> %a to <1 x double>
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ret <1 x double> %1
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}
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define double @v4f16_to_double(float, <4 x half> %a) #0 {
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; CHECK-LABEL: v4f16_to_double:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x half> %a to double
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ret double %1
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}
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define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 {
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; CHECK-LABEL: v4i16_to_v4f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x i16> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 {
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; CHECK-LABEL: v2i32_to_v4f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <2 x i32> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 {
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; CHECK-LABEL: v1i64_to_v4f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <1 x i64> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @i64_to_v4f16(float, i64 %a) #0 {
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; CHECK-LABEL: i64_to_v4f16:
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; CHECK: fmov d0, x0
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entry:
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%1 = bitcast i64 %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 {
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; CHECK-LABEL: v2float_to_v4f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <2 x float> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 {
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; CHECK-LABEL: v1double_to_v4f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <1 x double> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @double_to_v4f16(float, double %a) #0 {
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; CHECK-LABEL: double_to_v4f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast double %a to <4 x half>
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ret <4 x half> %1
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}
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define <8 x i16> @v8f16_to_v8i16(float, <8 x half> %a) #0 {
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; CHECK-LABEL: v8f16_to_v8i16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <8 x half> %a to <8 x i16>
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ret <8 x i16> %1
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}
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define <4 x i32> @v8f16_to_v4i32(float, <8 x half> %a) #0 {
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; CHECK-LABEL: v8f16_to_v4i32:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <8 x half> %a to <4 x i32>
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ret <4 x i32> %1
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}
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define <2 x i64> @v8f16_to_v2i64(float, <8 x half> %a) #0 {
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; CHECK-LABEL: v8f16_to_v2i64:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <8 x half> %a to <2 x i64>
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ret <2 x i64> %1
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}
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define <4 x float> @v8f16_to_v4float(float, <8 x half> %a) #0 {
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; CHECK-LABEL: v8f16_to_v4float:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <8 x half> %a to <4 x float>
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ret <4 x float> %1
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}
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define <2 x double> @v8f16_to_v2double(float, <8 x half> %a) #0 {
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; CHECK-LABEL: v8f16_to_v2double:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <8 x half> %a to <2 x double>
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ret <2 x double> %1
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}
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define <8 x half> @v8i16_to_v8f16(float, <8 x i16> %a) #0 {
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; CHECK-LABEL: v8i16_to_v8f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <8 x i16> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @v4i32_to_v8f16(float, <4 x i32> %a) #0 {
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; CHECK-LABEL: v4i32_to_v8f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x i32> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @v2i64_to_v8f16(float, <2 x i64> %a) #0 {
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; CHECK-LABEL: v2i64_to_v8f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <2 x i64> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @v4float_to_v8f16(float, <4 x float> %a) #0 {
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; CHECK-LABEL: v4float_to_v8f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <4 x float> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @v2double_to_v8f16(float, <2 x double> %a) #0 {
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; CHECK-LABEL: v2double_to_v8f16:
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; CHECK: mov v0.16b, v1.16b
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entry:
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%1 = bitcast <2 x double> %a to <8 x half>
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ret <8 x half> %1
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}
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