Tim Northover 6f86e23c1a AArch64/ARM64: support indexed loads/stores on vector types. ... While post-indexed LD1/ST1 instructions do exist for vector loads, this patch makes use of the more flexible addressing-modes in LDR/STR instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207838 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-02 14:54:15 +00:00
..
AArch64	AArch64/ARM64: print BFM instructions as BFI or BFXIL	2014-05-01 12:29:38 +00:00
ARM	ARM: support stack probe emission for Windows on ARM	2014-04-30 07:05:07 +00:00
ARM64	AArch64/ARM64: support indexed loads/stores on vector types.	2014-05-02 14:54:15 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon
Inputs
Mips	Add basic functionality for assignment of ints.	2014-05-01 20:39:21 +00:00
MSP430
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	[PowerPC] Fix rlwimi isel when mask is not constant	2014-04-13 17:10:58 +00:00
R600	R600/SI: Fix verifier error with pseudo store instructions.	2014-05-01 16:37:52 +00:00
SPARC	Revert "blockfreq: Temporarily turn on -debug-only=block-freq"	2014-04-19 22:45:44 +00:00
SystemZ
Thumb	Make this test not match its own filename, when being run from a path that includes the string 'add'.	2014-04-15 22:29:32 +00:00
Thumb2
X86	Allow SelectionDAG::FoldConstantArithmetic to work when it's called with a vector VT but scalar values.	2014-05-02 12:35:22 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00