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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.8 KiB
C++
63 lines
1.8 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIINSTRINFO_H
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#define SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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const SIRegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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/// \returns the encoding type of this instruction.
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unsigned getEncodingType(const MachineInstr &MI) const;
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/// \returns the size of this instructions encoding in number of bytes.
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unsigned getEncodingBytes(const MachineInstr &MI) const;
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virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const;
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virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
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virtual bool isMov(unsigned Opcode) const;
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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};
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} // End namespace llvm
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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NEED_WAIT = 1 << 4
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};
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}
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#endif //SIINSTRINFO_H
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