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https://github.com/c64scene-ar/llvm-6502.git
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87896d9368
Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
142 lines
3.5 KiB
LLVM
142 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARMv7A
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; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=ARMv7M
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define i32 @test1(i32 %x) {
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; ARMv7A: test1
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; ARMv7A: uxtb16 r0, r0
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; ARMv7M: test1
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; ARMv7M: bic r0, r0, #-16711936
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%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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; PR7503
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define i32 @test2(i32 %x) {
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; ARMv7A: test2
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; ARMv7A: uxtb16 r0, r0, ror #8
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; ARMv7M: test2
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, lsr #8
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%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
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ret i32 %tmp2
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}
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define i32 @test3(i32 %x) {
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; ARMv7A: test3
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; ARMv7A: uxtb16 r0, r0, ror #8
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; ARMv7M: test3
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, lsr #8
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%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
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ret i32 %tmp2
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}
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define i32 @test4(i32 %x) {
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; ARMv7A: test4
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; ARMv7A: uxtb16 r0, r0, ror #8
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; ARMv7M: test4
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, lsr #8
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%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
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%tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @test5(i32 %x) {
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; ARMv7A: test5
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; ARMv7A: uxtb16 r0, r0, ror #8
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; ARMv7M: test5
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, lsr #8
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%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
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ret i32 %tmp2
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}
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define i32 @test6(i32 %x) {
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; ARMv7A: test6
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; ARMv7A: uxtb16 r0, r0, ror #16
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; ARMv7M: test6
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, ror #16
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%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
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%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
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%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
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%tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @test7(i32 %x) {
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; ARMv7A: test7
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; ARMv7A: uxtb16 r0, r0, ror #16
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; ARMv7M: test7
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, ror #16
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%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
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%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
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%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
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%tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @test8(i32 %x) {
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; ARMv7A: test8
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; ARMv7A: uxtb16 r0, r0, ror #24
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; ARMv7M: test8
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, ror #24
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%tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
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%tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
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%tmp6 = or i32 %tmp2, %tmp5 ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @test9(i32 %x) {
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; ARMv7A: test9
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; ARMv7A: uxtb16 r0, r0, ror #24
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; ARMv7M: test9
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; ARMv7M: mov.w r1, #16711935
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; ARMv7M: and.w r0, r1, r0, ror #24
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%tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
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%tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
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%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
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%tmp6 = or i32 %tmp5, %tmp1 ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @test10(i32 %p0) {
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; ARMv7A: test10
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; ARMv7A: mov.w r1, #16253176
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; ARMv7A: and.w r0, r1, r0, lsr #7
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; ARMv7A: lsrs r1, r0, #5
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; ARMv7A: uxtb16 r1, r1
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; ARMv7A: orrs r0, r1
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; ARMv7M: test10
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; ARMv7M: mov.w r1, #16253176
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; ARMv7M: mov.w r2, #458759
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; ARMv7M: and.w r0, r1, r0, lsr #7
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; ARMv7M: and.w r1, r2, r0, lsr #5
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; ARMv7M: orrs r0, r1
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%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
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%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
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%tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]
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%tmp5 = and i32 %tmp4, 458759 ; <i32> [#uses=1]
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%tmp7 = or i32 %tmp5, %tmp2 ; <i32> [#uses=1]
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ret i32 %tmp7
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}
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